xref: /linux/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml (revision 8ffe772076bbb6828e28705bda93ac37c8d7294c) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - google,gs101-usb31drd-phy
29      - samsung,exynos5250-usbdrd-phy
30      - samsung,exynos5420-usbdrd-phy
31      - samsung,exynos5433-usbdrd-phy
32      - samsung,exynos7-usbdrd-phy
33      - samsung,exynos850-usbdrd-phy
34
35  clocks:
36    minItems: 2
37    maxItems: 5
38
39  clock-names:
40    minItems: 2
41    maxItems: 5
42    description: |
43      At least two clocks::
44        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
45          for register access.
46        - PHY reference clock (usually crystal clock), used for PHY operations,
47          associated by phy name. It is used to determine bit values for clock
48          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
49          in the CMU.
50
51  "#phy-cells":
52    const: 1
53
54  port:
55    $ref: /schemas/graph.yaml#/properties/port
56    description:
57      Any connector to the data bus of this controller should be modelled using
58      the OF graph bindings specified.
59
60  reg:
61    minItems: 1
62    maxItems: 3
63
64  reg-names:
65    minItems: 1
66    items:
67      - const: phy
68      - const: pcs
69      - const: pma
70
71  samsung,pmu-syscon:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      Phandle to PMU system controller interface.
75
76  vbus-supply:
77    description:
78      VBUS power source.
79
80  vbus-boost-supply:
81    description:
82      VBUS Boost 5V power source.
83
84  pll-supply:
85    description: Power supply for the USB PLL.
86
87  dvdd-usb20-supply:
88    description: DVDD power supply for the USB 2.0 phy.
89
90  vddh-usb20-supply:
91    description: VDDh power supply for the USB 2.0 phy.
92
93  vdd33-usb20-supply:
94    description: 3.3V power supply for the USB 2.0 phy.
95
96  vdda-usbdp-supply:
97    description: VDDa power supply for the USB DP phy.
98
99  vddh-usbdp-supply:
100    description: VDDh power supply for the USB DP phy.
101
102required:
103  - compatible
104  - clocks
105  - clock-names
106  - "#phy-cells"
107  - reg
108  - samsung,pmu-syscon
109
110allOf:
111  - if:
112      properties:
113        compatible:
114          contains:
115            const: google,gs101-usb31drd-phy
116    then:
117      $ref: /schemas/usb/usb-switch.yaml#
118
119      properties:
120        clocks:
121          items:
122            - description: Gate of main PHY clock
123            - description: Gate of PHY reference clock
124            - description: Gate of control interface AXI clock
125            - description: Gate of control interface APB clock
126            - description: Gate of SCL APB clock
127
128        clock-names:
129          items:
130            - const: phy
131            - const: ref
132            - const: ctrl_aclk
133            - const: ctrl_pclk
134            - const: scl_pclk
135
136        reg:
137          minItems: 3
138
139        reg-names:
140          minItems: 3
141
142      required:
143        - reg-names
144        - orientation-switch
145        - port
146        - pll-supply
147        - dvdd-usb20-supply
148        - vddh-usb20-supply
149        - vdd33-usb20-supply
150        - vdda-usbdp-supply
151        - vddh-usbdp-supply
152
153  - if:
154      properties:
155        compatible:
156          contains:
157            enum:
158              - samsung,exynos5433-usbdrd-phy
159              - samsung,exynos7-usbdrd-phy
160    then:
161      properties:
162        clocks:
163          minItems: 5
164          maxItems: 5
165
166        clock-names:
167          items:
168            - const: phy
169            - const: ref
170            - const: phy_utmi
171            - const: phy_pipe
172            - const: itp
173
174        reg:
175          maxItems: 1
176
177        reg-names:
178          maxItems: 1
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - samsung,exynos5250-usbdrd-phy
186              - samsung,exynos5420-usbdrd-phy
187              - samsung,exynos850-usbdrd-phy
188    then:
189      properties:
190        clocks:
191          minItems: 2
192          maxItems: 2
193
194        clock-names:
195          items:
196            - const: phy
197            - const: ref
198
199        reg:
200          maxItems: 1
201
202        reg-names:
203          maxItems: 1
204
205unevaluatedProperties: false
206
207examples:
208  - |
209    #include <dt-bindings/clock/exynos5420.h>
210
211    phy@12100000 {
212        compatible = "samsung,exynos5420-usbdrd-phy";
213        reg = <0x12100000 0x100>;
214        #phy-cells = <1>;
215        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
216        clock-names = "phy", "ref";
217        samsung,pmu-syscon = <&pmu_system_controller>;
218        vbus-supply = <&usb300_vbus_reg>;
219    };
220