xref: /linux/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml (revision 8d2c2fa2209e83d0eb10f7330d8a0bbdc1df32ff) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - google,gs101-usb31drd-phy
29      - samsung,exynos2200-usb32drd-phy
30      - samsung,exynos5250-usbdrd-phy
31      - samsung,exynos5420-usbdrd-phy
32      - samsung,exynos5433-usbdrd-phy
33      - samsung,exynos7-usbdrd-phy
34      - samsung,exynos7870-usbdrd-phy
35      - samsung,exynos850-usbdrd-phy
36
37  clocks:
38    minItems: 1
39    maxItems: 5
40
41  clock-names:
42    minItems: 1
43    maxItems: 5
44    description: |
45      Typically two clocks:
46        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
47          for register access.
48        - PHY reference clock (usually crystal clock), used for PHY operations,
49          associated by phy name. It is used to determine bit values for clock
50          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
51          in the CMU. It's not needed for Exynos2200.
52
53  "#phy-cells":
54    const: 1
55
56  phys:
57    maxItems: 1
58    description:
59      USBDRD-underlying high-speed PHY
60
61  phy-names:
62    const: hs
63
64  port:
65    $ref: /schemas/graph.yaml#/properties/port
66    description:
67      Any connector to the data bus of this controller should be modelled using
68      the OF graph bindings specified.
69
70  reg:
71    minItems: 1
72    maxItems: 3
73
74  reg-names:
75    minItems: 1
76    items:
77      - const: phy
78      - const: pcs
79      - const: pma
80
81  samsung,pmu-syscon:
82    $ref: /schemas/types.yaml#/definitions/phandle
83    description:
84      Phandle to PMU system controller interface.
85
86  vbus-supply:
87    description:
88      VBUS power source.
89
90  vbus-boost-supply:
91    description:
92      VBUS Boost 5V power source.
93
94  pll-supply:
95    description: Power supply for the USB PLL.
96
97  dvdd-usb20-supply:
98    description: DVDD power supply for the USB 2.0 phy.
99
100  vddh-usb20-supply:
101    description: VDDh power supply for the USB 2.0 phy.
102
103  vdd33-usb20-supply:
104    description: 3.3V power supply for the USB 2.0 phy.
105
106  vdda-usbdp-supply:
107    description: VDDa power supply for the USB DP phy.
108
109  vddh-usbdp-supply:
110    description: VDDh power supply for the USB DP phy.
111
112required:
113  - compatible
114  - clocks
115  - clock-names
116  - "#phy-cells"
117  - reg
118  - samsung,pmu-syscon
119
120allOf:
121  - if:
122      properties:
123        compatible:
124          contains:
125            const: google,gs101-usb31drd-phy
126    then:
127      $ref: /schemas/usb/usb-switch.yaml#
128
129      properties:
130        clocks:
131          items:
132            - description: Gate of main PHY clock
133            - description: Gate of PHY reference clock
134            - description: Gate of control interface AXI clock
135            - description: Gate of control interface APB clock
136            - description: Gate of SCL APB clock
137
138        clock-names:
139          items:
140            - const: phy
141            - const: ref
142            - const: ctrl_aclk
143            - const: ctrl_pclk
144            - const: scl_pclk
145
146        reg:
147          minItems: 3
148
149        reg-names:
150          minItems: 3
151
152      required:
153        - reg-names
154        - orientation-switch
155        - port
156        - pll-supply
157        - dvdd-usb20-supply
158        - vddh-usb20-supply
159        - vdd33-usb20-supply
160        - vdda-usbdp-supply
161        - vddh-usbdp-supply
162
163  - if:
164      properties:
165        compatible:
166          contains:
167            enum:
168              - samsung,exynos2200-usb32drd-phy
169    then:
170      properties:
171        clocks:
172          maxItems: 1
173        clock-names:
174          items:
175            - const: phy
176        reg:
177          maxItems: 1
178        reg-names:
179          maxItems: 1
180      required:
181        - phys
182        - phy-names
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - samsung,exynos5433-usbdrd-phy
190              - samsung,exynos7-usbdrd-phy
191    then:
192      properties:
193        clocks:
194          minItems: 5
195          maxItems: 5
196
197        clock-names:
198          items:
199            - const: phy
200            - const: ref
201            - const: phy_utmi
202            - const: phy_pipe
203            - const: itp
204
205        reg:
206          maxItems: 1
207
208        reg-names:
209          maxItems: 1
210
211  - if:
212      properties:
213        compatible:
214          contains:
215            enum:
216              - samsung,exynos5250-usbdrd-phy
217              - samsung,exynos5420-usbdrd-phy
218              - samsung,exynos7870-usbdrd-phy
219              - samsung,exynos850-usbdrd-phy
220    then:
221      properties:
222        clocks:
223          minItems: 2
224          maxItems: 2
225
226        clock-names:
227          items:
228            - const: phy
229            - const: ref
230
231        reg:
232          maxItems: 1
233
234        reg-names:
235          maxItems: 1
236
237unevaluatedProperties: false
238
239examples:
240  - |
241    #include <dt-bindings/clock/exynos5420.h>
242
243    phy@12100000 {
244        compatible = "samsung,exynos5420-usbdrd-phy";
245        reg = <0x12100000 0x100>;
246        #phy-cells = <1>;
247        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
248        clock-names = "phy", "ref";
249        samsung,pmu-syscon = <&pmu_system_controller>;
250        vbus-supply = <&usb300_vbus_reg>;
251    };
252