xref: /linux/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml (revision 36ec807b627b4c0a0a382f0ae48eac7187d14b2b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - google,gs101-usb31drd-phy
29      - samsung,exynos5250-usbdrd-phy
30      - samsung,exynos5420-usbdrd-phy
31      - samsung,exynos5433-usbdrd-phy
32      - samsung,exynos7-usbdrd-phy
33      - samsung,exynos850-usbdrd-phy
34
35  clocks:
36    minItems: 2
37    maxItems: 5
38
39  clock-names:
40    minItems: 2
41    maxItems: 5
42    description: |
43      At least two clocks::
44        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
45          for register access.
46        - PHY reference clock (usually crystal clock), used for PHY operations,
47          associated by phy name. It is used to determine bit values for clock
48          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
49          in the CMU.
50
51  "#phy-cells":
52    const: 1
53
54  port:
55    $ref: /schemas/graph.yaml#/properties/port
56    description:
57      Any connector to the data bus of this controller should be modelled using
58      the OF graph bindings specified.
59
60  reg:
61    minItems: 1
62    maxItems: 3
63
64  reg-names:
65    minItems: 1
66    items:
67      - const: phy
68      - const: pcs
69      - const: pma
70
71  samsung,pmu-syscon:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      Phandle to PMU system controller interface.
75
76  vbus-supply:
77    description:
78      VBUS power source.
79
80  vbus-boost-supply:
81    description:
82      VBUS Boost 5V power source.
83
84  pll-supply:
85    description: Power supply for the USB PLL.
86  dvdd-usb20-supply:
87    description: DVDD power supply for the USB 2.0 phy.
88  vddh-usb20-supply:
89    description: VDDh power supply for the USB 2.0 phy.
90  vdd33-usb20-supply:
91    description: 3.3V power supply for the USB 2.0 phy.
92  vdda-usbdp-supply:
93    description: VDDa power supply for the USB DP phy.
94  vddh-usbdp-supply:
95    description: VDDh power supply for the USB DP phy.
96
97required:
98  - compatible
99  - clocks
100  - clock-names
101  - "#phy-cells"
102  - reg
103  - samsung,pmu-syscon
104
105allOf:
106  - if:
107      properties:
108        compatible:
109          contains:
110            const: google,gs101-usb31drd-phy
111    then:
112      properties:
113        clocks:
114          items:
115            - description: Gate of main PHY clock
116            - description: Gate of PHY reference clock
117            - description: Gate of control interface AXI clock
118            - description: Gate of control interface APB clock
119            - description: Gate of SCL APB clock
120        clock-names:
121          items:
122            - const: phy
123            - const: ref
124            - const: ctrl_aclk
125            - const: ctrl_pclk
126            - const: scl_pclk
127        reg:
128          minItems: 3
129        reg-names:
130          minItems: 3
131      required:
132        - reg-names
133        - pll-supply
134        - dvdd-usb20-supply
135        - vddh-usb20-supply
136        - vdd33-usb20-supply
137        - vdda-usbdp-supply
138        - vddh-usbdp-supply
139
140  - if:
141      properties:
142        compatible:
143          contains:
144            enum:
145              - samsung,exynos5433-usbdrd-phy
146              - samsung,exynos7-usbdrd-phy
147    then:
148      properties:
149        clocks:
150          minItems: 5
151          maxItems: 5
152        clock-names:
153          items:
154            - const: phy
155            - const: ref
156            - const: phy_utmi
157            - const: phy_pipe
158            - const: itp
159        reg:
160          maxItems: 1
161        reg-names:
162          maxItems: 1
163
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - samsung,exynos5250-usbdrd-phy
170              - samsung,exynos5420-usbdrd-phy
171              - samsung,exynos850-usbdrd-phy
172    then:
173      properties:
174        clocks:
175          minItems: 2
176          maxItems: 2
177        clock-names:
178          items:
179            - const: phy
180            - const: ref
181        reg:
182          maxItems: 1
183        reg-names:
184          maxItems: 1
185
186additionalProperties: false
187
188examples:
189  - |
190    #include <dt-bindings/clock/exynos5420.h>
191
192    phy@12100000 {
193        compatible = "samsung,exynos5420-usbdrd-phy";
194        reg = <0x12100000 0x100>;
195        #phy-cells = <1>;
196        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
197        clock-names = "phy", "ref";
198        samsung,pmu-syscon = <&pmu_system_controller>;
199        vbus-supply = <&usb300_vbus_reg>;
200    };
201