xref: /linux/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml (revision 36f353a1ebf88280f58d1ebfe2731251d9159456) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
8
9maintainers:
10  - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3588-hdptx-phy
16
17  reg:
18    maxItems: 1
19
20  clocks:
21    items:
22      - description: Reference clock
23      - description: APB clock
24
25  clock-names:
26    items:
27      - const: ref
28      - const: apb
29
30  "#phy-cells":
31    const: 0
32
33  resets:
34    items:
35      - description: PHY reset line
36      - description: APB reset line
37      - description: INIT reset line
38      - description: CMN reset line
39      - description: LANE reset line
40      - description: ROPLL reset line
41      - description: LCPLL reset line
42
43  reset-names:
44    items:
45      - const: phy
46      - const: apb
47      - const: init
48      - const: cmn
49      - const: lane
50      - const: ropll
51      - const: lcpll
52
53  rockchip,grf:
54    $ref: /schemas/types.yaml#/definitions/phandle
55    description: Some PHY related data is accessed through GRF regs.
56
57required:
58  - compatible
59  - reg
60  - clocks
61  - clock-names
62  - "#phy-cells"
63  - resets
64  - reset-names
65  - rockchip,grf
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
72    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
73
74    soc {
75      #address-cells = <2>;
76      #size-cells = <2>;
77
78      phy@fed60000 {
79        compatible = "rockchip,rk3588-hdptx-phy";
80        reg = <0x0 0xfed60000 0x0 0x2000>;
81        clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
82        clock-names = "ref", "apb";
83        #phy-cells = <0>;
84        resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
85                 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
86                 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
87                 <&cru SRST_HDPTX0_LCPLL>;
88        reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
89        rockchip,grf = <&hdptxphy_grf>;
90      };
91    };
92