xref: /linux/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml (revision e291c116f60f3c1ca98090f0f8e7c77e658562fb) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip MIPI DPHY with additional LVDS/TTL modes
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  "#phy-cells":
14    const: 0
15
16  compatible:
17    enum:
18      - rockchip,px30-dsi-dphy
19      - rockchip,rk3128-dsi-dphy
20      - rockchip,rk3368-dsi-dphy
21      - rockchip,rk3568-dsi-dphy
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    items:
28      - description: PLL reference clock
29      - description: Module clock
30
31  clock-names:
32    items:
33      - const: ref
34      - const: pclk
35
36  power-domains:
37    maxItems: 1
38    description: phandle to the associated power domain
39
40  resets:
41    items:
42      - description: exclusive PHY reset line
43
44  reset-names:
45    items:
46      - const: apb
47
48required:
49  - "#phy-cells"
50  - compatible
51  - reg
52  - clocks
53  - clock-names
54  - resets
55  - reset-names
56
57additionalProperties: false
58
59examples:
60  - |
61    dsi_dphy: phy@ff2e0000 {
62        compatible = "rockchip,px30-dsi-dphy";
63        reg = <0xff2e0000 0x10000>;
64        clocks = <&pmucru 13>, <&cru 12>;
65        clock-names = "ref", "pclk";
66        resets = <&cru 12>;
67        reset-names = "apb";
68        #phy-cells = <0>;
69    };
70
71...
72