xref: /linux/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml (revision df9c299371054cb725eef730fd0f1d0fe2ed6bb0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car generation 3 USB 2.0 PHY
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - renesas,usb2-phy-r8a77470  # RZ/G1C
18              - renesas,usb2-phy-r9a08g045 # RZ/G3S
19              - renesas,usb2-phy-r9a09g057 # RZ/V2H(P)
20
21      - items:
22          - enum:
23              - renesas,usb2-phy-r7s9210  # RZ/A2
24              - renesas,usb2-phy-r8a774a1 # RZ/G2M
25              - renesas,usb2-phy-r8a774b1 # RZ/G2N
26              - renesas,usb2-phy-r8a774c0 # RZ/G2E
27              - renesas,usb2-phy-r8a774e1 # RZ/G2H
28              - renesas,usb2-phy-r8a7795  # R-Car H3
29              - renesas,usb2-phy-r8a7796  # R-Car M3-W
30              - renesas,usb2-phy-r8a77961 # R-Car M3-W+
31              - renesas,usb2-phy-r8a77965 # R-Car M3-N
32              - renesas,usb2-phy-r8a77990 # R-Car E3
33              - renesas,usb2-phy-r8a77995 # R-Car D3
34          - const: renesas,rcar-gen3-usb2-phy
35
36      - items:
37          - enum:
38              - renesas,usb2-phy-r9a07g043 # RZ/G2UL
39              - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
40              - renesas,usb2-phy-r9a07g054 # RZ/V2L
41          - const: renesas,rzg2l-usb2-phy
42
43  reg:
44    maxItems: 1
45
46  clocks:
47    minItems: 1
48    maxItems: 2
49
50  clock-names:
51    minItems: 1
52    items:
53      - const: fck
54      - const: usb_x1
55
56  '#phy-cells':
57    enum: [0, 1]  # and 0 is deprecated.
58    description: |
59      The phandle's argument in the PHY specifier is the INT_STATUS bit of
60      controller.
61      - 1 = USBH_INTA (OHCI)
62      - 2 = USBH_INTB (EHCI)
63      - 3 = UCOM_INT (OTG and BC)
64
65  interrupts:
66    maxItems: 1
67
68  power-domains:
69    maxItems: 1
70
71  resets:
72    minItems: 1
73    items:
74      - description: reset of USB 2.0 host side
75      - description: reset of USB 2.0 peripheral side
76
77  vbus-supply:
78    description: |
79      Phandle to a regulator that provides power to the VBUS. This regulator
80      will be managed during the PHY power on/off sequence.
81
82  renesas,no-otg-pins:
83    $ref: /schemas/types.yaml#/definitions/flag
84    description: |
85      specify when a board does not provide proper otg pins.
86
87  dr_mode: true
88
89if:
90  properties:
91    compatible:
92      contains:
93        const: renesas,usb2-phy-r7s9210
94then:
95  required:
96    - clock-names
97
98required:
99  - compatible
100  - reg
101  - clocks
102  - '#phy-cells'
103
104allOf:
105  - if:
106      properties:
107        compatible:
108          contains:
109            enum:
110              - renesas,usb2-phy-r9a09g057
111              - renesas,rzg2l-usb2-phy
112    then:
113      properties:
114        clocks:
115          minItems: 2
116      required:
117        - resets
118
119additionalProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
124    #include <dt-bindings/interrupt-controller/arm-gic.h>
125    #include <dt-bindings/power/r8a7795-sysc.h>
126
127    usb-phy@ee080200 {
128        compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
129        reg = <0xee080200 0x700>;
130        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
131        clocks = <&cpg CPG_MOD 703>;
132        #phy-cells = <1>;
133    };
134
135    usb-phy@ee0a0200 {
136        compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
137        reg = <0xee0a0200 0x700>;
138        clocks = <&cpg CPG_MOD 702>;
139        #phy-cells = <1>;
140    };
141