1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car generation 3 USB 2.0 PHY 8 9maintainers: 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,usb2-phy-r8a77470 # RZ/G1C 18 - renesas,usb2-phy-r9a08g045 # RZ/G3S 19 - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) 20 21 - items: 22 - enum: 23 - renesas,usb2-phy-r7s9210 # RZ/A2 24 - renesas,usb2-phy-r8a774a1 # RZ/G2M 25 - renesas,usb2-phy-r8a774b1 # RZ/G2N 26 - renesas,usb2-phy-r8a774c0 # RZ/G2E 27 - renesas,usb2-phy-r8a774e1 # RZ/G2H 28 - renesas,usb2-phy-r8a7795 # R-Car H3 29 - renesas,usb2-phy-r8a7796 # R-Car M3-W 30 - renesas,usb2-phy-r8a77961 # R-Car M3-W+ 31 - renesas,usb2-phy-r8a77965 # R-Car M3-N 32 - renesas,usb2-phy-r8a77990 # R-Car E3 33 - renesas,usb2-phy-r8a77995 # R-Car D3 34 - const: renesas,rcar-gen3-usb2-phy 35 36 - items: 37 - enum: 38 - renesas,usb2-phy-r9a07g043 # RZ/G2UL 39 - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} 40 - renesas,usb2-phy-r9a07g054 # RZ/V2L 41 - const: renesas,rzg2l-usb2-phy 42 43 - items: 44 - const: renesas,usb2-phy-r9a09g056 # RZ/V2N 45 - const: renesas,usb2-phy-r9a09g057 46 47 - const: renesas,usb2-phy-r9a09g077 # RZ/T2H 48 49 - items: 50 - const: renesas,usb2-phy-r9a09g087 # RZ/N2H 51 - const: renesas,usb2-phy-r9a09g077 52 53 reg: 54 maxItems: 1 55 56 clocks: 57 minItems: 1 58 maxItems: 2 59 60 clock-names: 61 minItems: 1 62 items: 63 - const: fck 64 - const: usb_x1 65 66 '#phy-cells': 67 enum: [0, 1] # and 0 is deprecated. 68 description: | 69 The phandle's argument in the PHY specifier is the INT_STATUS bit of 70 controller. 71 - 1 = USBH_INTA (OHCI) 72 - 2 = USBH_INTB (EHCI) 73 - 3 = UCOM_INT (OTG and BC) 74 75 interrupts: 76 maxItems: 1 77 78 power-domains: 79 maxItems: 1 80 81 resets: 82 minItems: 1 83 items: 84 - description: reset of USB 2.0 host side 85 - description: reset of USB 2.0 peripheral side 86 87 vbus-supply: 88 description: | 89 Phandle to a regulator that provides power to the VBUS. This regulator 90 will be managed during the PHY power on/off sequence. 91 92 renesas,no-otg-pins: 93 $ref: /schemas/types.yaml#/definitions/flag 94 description: | 95 specify when a board does not provide proper otg pins. 96 97 dr_mode: true 98 99if: 100 properties: 101 compatible: 102 contains: 103 const: renesas,usb2-phy-r7s9210 104then: 105 required: 106 - clock-names 107 108required: 109 - compatible 110 - reg 111 - clocks 112 - '#phy-cells' 113 114allOf: 115 - if: 116 properties: 117 compatible: 118 contains: 119 enum: 120 - renesas,usb2-phy-r9a09g057 121 - renesas,usb2-phy-r9a08g045 122 - renesas,rzg2l-usb2-phy 123 then: 124 properties: 125 clocks: 126 minItems: 2 127 required: 128 - resets 129 130 - if: 131 properties: 132 compatible: 133 contains: 134 const: renesas,usb2-phy-r9a09g077 135 then: 136 properties: 137 clocks: 138 minItems: 2 139 resets: false 140 141additionalProperties: false 142 143examples: 144 - | 145 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 146 #include <dt-bindings/interrupt-controller/arm-gic.h> 147 #include <dt-bindings/power/r8a7795-sysc.h> 148 149 usb-phy@ee080200 { 150 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 151 reg = <0xee080200 0x700>; 152 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&cpg CPG_MOD 703>; 154 #phy-cells = <1>; 155 }; 156 157 usb-phy@ee0a0200 { 158 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 159 reg = <0xee0a0200 0x700>; 160 clocks = <&cpg CPG_MOD 702>; 161 #phy-cells = <1>; 162 }; 163