1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car generation 3 USB 2.0 PHY 8 9maintainers: 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,usb2-phy-r8a77470 # RZ/G1C 18 - renesas,usb2-phy-r9a08g045 # RZ/G3S 19 - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) 20 21 - items: 22 - enum: 23 - renesas,usb2-phy-r7s9210 # RZ/A2 24 - renesas,usb2-phy-r8a774a1 # RZ/G2M 25 - renesas,usb2-phy-r8a774b1 # RZ/G2N 26 - renesas,usb2-phy-r8a774c0 # RZ/G2E 27 - renesas,usb2-phy-r8a774e1 # RZ/G2H 28 - renesas,usb2-phy-r8a7795 # R-Car H3 29 - renesas,usb2-phy-r8a7796 # R-Car M3-W 30 - renesas,usb2-phy-r8a77961 # R-Car M3-W+ 31 - renesas,usb2-phy-r8a77965 # R-Car M3-N 32 - renesas,usb2-phy-r8a77990 # R-Car E3 33 - renesas,usb2-phy-r8a77995 # R-Car D3 34 - const: renesas,rcar-gen3-usb2-phy 35 36 - items: 37 - enum: 38 - renesas,usb2-phy-r9a07g043 # RZ/G2UL 39 - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} 40 - renesas,usb2-phy-r9a07g054 # RZ/V2L 41 - const: renesas,rzg2l-usb2-phy 42 43 - items: 44 - enum: 45 - renesas,usb2-phy-r9a09g047 # RZ/G3E 46 - renesas,usb2-phy-r9a09g056 # RZ/V2N 47 - const: renesas,usb2-phy-r9a09g057 48 49 - const: renesas,usb2-phy-r9a09g077 # RZ/T2H 50 51 - items: 52 - const: renesas,usb2-phy-r9a09g087 # RZ/N2H 53 - const: renesas,usb2-phy-r9a09g077 54 55 reg: 56 maxItems: 1 57 58 clocks: 59 minItems: 1 60 maxItems: 2 61 62 clock-names: 63 minItems: 1 64 items: 65 - const: fck 66 - const: usb_x1 67 68 '#phy-cells': 69 enum: [0, 1] # and 0 is deprecated. 70 description: | 71 The phandle's argument in the PHY specifier is the INT_STATUS bit of 72 controller. 73 - 1 = USBH_INTA (OHCI) 74 - 2 = USBH_INTB (EHCI) 75 - 3 = UCOM_INT (OTG and BC) 76 77 interrupts: 78 maxItems: 1 79 80 power-domains: 81 maxItems: 1 82 83 resets: 84 minItems: 1 85 items: 86 - description: reset of USB 2.0 host side 87 - description: reset of USB 2.0 peripheral side 88 89 vbus-supply: 90 description: | 91 Phandle to a regulator that provides power to the VBUS. This regulator 92 will be managed during the PHY power on/off sequence. 93 94 vbus-regulator: 95 $ref: /schemas/regulator/regulator.yaml# 96 description: USB VBUS internal regulator 97 type: object 98 unevaluatedProperties: false 99 100 renesas,no-otg-pins: 101 $ref: /schemas/types.yaml#/definitions/flag 102 description: | 103 specify when a board does not provide proper otg pins. 104 105 dr_mode: true 106 107 mux-states: 108 description: 109 phandle to a mux controller node that select the source for USB VBUS. 110 maxItems: 1 111 112if: 113 properties: 114 compatible: 115 contains: 116 const: renesas,usb2-phy-r7s9210 117then: 118 required: 119 - clock-names 120 121required: 122 - compatible 123 - reg 124 - clocks 125 - '#phy-cells' 126 127allOf: 128 - if: 129 properties: 130 compatible: 131 contains: 132 enum: 133 - renesas,usb2-phy-r9a09g057 134 - renesas,usb2-phy-r9a08g045 135 - renesas,rzg2l-usb2-phy 136 then: 137 properties: 138 clocks: 139 minItems: 2 140 required: 141 - resets 142 143 - if: 144 properties: 145 compatible: 146 contains: 147 const: renesas,usb2-phy-r9a09g077 148 then: 149 properties: 150 clocks: 151 minItems: 2 152 resets: false 153 154additionalProperties: false 155 156examples: 157 - | 158 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 159 #include <dt-bindings/interrupt-controller/arm-gic.h> 160 #include <dt-bindings/power/r8a7795-sysc.h> 161 162 usb-phy@ee080200 { 163 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 164 reg = <0xee080200 0x700>; 165 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cpg CPG_MOD 703>; 167 #phy-cells = <1>; 168 }; 169 170 usb-phy@ee0a0200 { 171 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 172 reg = <0xee0a0200 0x700>; 173 clocks = <&cpg CPG_MOD 702>; 174 #phy-cells = <1>; 175 }; 176