1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car generation 3 USB 2.0 PHY 8 9maintainers: 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,usb2-phy-r8a77470 # RZ/G1C 18 - renesas,usb2-phy-r9a08g045 # RZ/G3S 19 - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) 20 21 - items: 22 - enum: 23 - renesas,usb2-phy-r7s9210 # RZ/A2 24 - renesas,usb2-phy-r8a774a1 # RZ/G2M 25 - renesas,usb2-phy-r8a774b1 # RZ/G2N 26 - renesas,usb2-phy-r8a774c0 # RZ/G2E 27 - renesas,usb2-phy-r8a774e1 # RZ/G2H 28 - renesas,usb2-phy-r8a7795 # R-Car H3 29 - renesas,usb2-phy-r8a7796 # R-Car M3-W 30 - renesas,usb2-phy-r8a77961 # R-Car M3-W+ 31 - renesas,usb2-phy-r8a77965 # R-Car M3-N 32 - renesas,usb2-phy-r8a77990 # R-Car E3 33 - renesas,usb2-phy-r8a77995 # R-Car D3 34 - const: renesas,rcar-gen3-usb2-phy 35 36 - items: 37 - enum: 38 - renesas,usb2-phy-r9a07g043 # RZ/G2UL 39 - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} 40 - renesas,usb2-phy-r9a07g054 # RZ/V2L 41 - const: renesas,rzg2l-usb2-phy 42 43 - items: 44 - const: renesas,usb2-phy-r9a09g056 # RZ/V2N 45 - const: renesas,usb2-phy-r9a09g057 46 47 reg: 48 maxItems: 1 49 50 clocks: 51 minItems: 1 52 maxItems: 2 53 54 clock-names: 55 minItems: 1 56 items: 57 - const: fck 58 - const: usb_x1 59 60 '#phy-cells': 61 enum: [0, 1] # and 0 is deprecated. 62 description: | 63 The phandle's argument in the PHY specifier is the INT_STATUS bit of 64 controller. 65 - 1 = USBH_INTA (OHCI) 66 - 2 = USBH_INTB (EHCI) 67 - 3 = UCOM_INT (OTG and BC) 68 69 interrupts: 70 maxItems: 1 71 72 power-domains: 73 maxItems: 1 74 75 resets: 76 minItems: 1 77 items: 78 - description: reset of USB 2.0 host side 79 - description: reset of USB 2.0 peripheral side 80 81 vbus-supply: 82 description: | 83 Phandle to a regulator that provides power to the VBUS. This regulator 84 will be managed during the PHY power on/off sequence. 85 86 renesas,no-otg-pins: 87 $ref: /schemas/types.yaml#/definitions/flag 88 description: | 89 specify when a board does not provide proper otg pins. 90 91 dr_mode: true 92 93if: 94 properties: 95 compatible: 96 contains: 97 const: renesas,usb2-phy-r7s9210 98then: 99 required: 100 - clock-names 101 102required: 103 - compatible 104 - reg 105 - clocks 106 - '#phy-cells' 107 108allOf: 109 - if: 110 properties: 111 compatible: 112 contains: 113 enum: 114 - renesas,usb2-phy-r9a09g057 115 - renesas,rzg2l-usb2-phy 116 then: 117 properties: 118 clocks: 119 minItems: 2 120 required: 121 - resets 122 123additionalProperties: false 124 125examples: 126 - | 127 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 128 #include <dt-bindings/interrupt-controller/arm-gic.h> 129 #include <dt-bindings/power/r8a7795-sysc.h> 130 131 usb-phy@ee080200 { 132 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 133 reg = <0xee080200 0x700>; 134 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cpg CPG_MOD 703>; 136 #phy-cells = <1>; 137 }; 138 139 usb-phy@ee0a0200 { 140 compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; 141 reg = <0xee0a0200 0x700>; 142 clocks = <&cpg CPG_MOD 702>; 143 #phy-cells = <1>; 144 }; 145