xref: /linux/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml (revision a3f9e4bc1ec9d8f1e352eb7c1cbaea3168246be7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2023 Realtek Semiconductor Corporation
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Realtek DHC SoCs USB 3.0 PHY
9
10maintainers:
11  - Stanley Chang <stanley_chang@realtek.com>
12
13description: |
14  Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
15  The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
16  support multiple XHCI controllers. One PHY device node maps to one XHCI
17  controller.
18
19  RTD1295/RTD1619 SoCs USB
20  The USB architecture includes three XHCI controllers.
21  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
22  controllers.
23  XHCI controller#0 -- usb2phy -- phy#0
24                    |- usb3phy -- phy#0
25  XHCI controller#1 -- usb2phy -- phy#0
26  XHCI controller#2 -- usb2phy -- phy#0
27                    |- usb3phy -- phy#0
28
29  RTD1319/RTD1619b SoCs USB
30  The USB architecture includes three XHCI controllers.
31  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
32  XHCI controller#0 -- usb2phy -- phy#0
33  XHCI controller#1 -- usb2phy -- phy#0
34  XHCI controller#2 -- usb2phy -- phy#0
35                    |- usb3phy -- phy#0
36
37  RTD1319d SoCs USB
38  The USB architecture includes three XHCI controllers.
39  Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
40  XHCI controller#0 -- usb2phy -- phy#0
41                    |- usb3phy -- phy#0
42  XHCI controller#1 -- usb2phy -- phy#0
43  XHCI controller#2 -- usb2phy -- phy#0
44
45properties:
46  compatible:
47    enum:
48      - realtek,rtd1295-usb3phy
49      - realtek,rtd1319-usb3phy
50      - realtek,rtd1319d-usb3phy
51      - realtek,rtd1619-usb3phy
52      - realtek,rtd1619b-usb3phy
53
54  reg:
55    maxItems: 1
56
57  "#phy-cells":
58    const: 0
59
60  nvmem-cells:
61    maxItems: 1
62    description: A phandle to the tx lfps swing trim data provided by
63      a nvmem device, if unspecified, default values shall be used.
64
65  nvmem-cell-names:
66    items:
67      - const: usb_u3_tx_lfps_swing_trim
68
69  realtek,amplitude-control-coarse-tuning:
70    description:
71      This adjusts the signal amplitude for normal operation and beacon LFPS.
72      This value is a parameter for coarse tuning.
73      For different boards, if the default value is inappropriate, this
74      property can be assigned to adjust.
75    $ref: /schemas/types.yaml#/definitions/uint32
76    default: 255
77    minimum: 0
78    maximum: 255
79
80  realtek,amplitude-control-fine-tuning:
81    description:
82      This adjusts the signal amplitude for normal operation and beacon LFPS.
83      This value is used for fine-tuning parameters.
84    $ref: /schemas/types.yaml#/definitions/uint32
85    default: 65535
86    minimum: 0
87    maximum: 65535
88
89required:
90  - compatible
91  - reg
92  - "#phy-cells"
93
94additionalProperties: false
95
96examples:
97  - |
98    usb-phy@13e10 {
99        compatible = "realtek,rtd1319d-usb3phy";
100        reg = <0x13e10 0x4>;
101        #phy-cells = <0>;
102
103        nvmem-cells = <&otp_usb_u3_tx_lfps_swing_trim>;
104        nvmem-cell-names = "usb_u3_tx_lfps_swing_trim";
105
106        realtek,amplitude-control-coarse-tuning = <0x77>;
107    };
108