xref: /linux/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml (revision 79d2e1919a2728ef49d938eb20ebd5903c14dfb0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SNPS eUSB2 phy controller
8
9maintainers:
10  - Abel Vesa <abel.vesa@linaro.org>
11
12description:
13  eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,sar2130p-snps-eusb2-phy
21              - qcom,sdx75-snps-eusb2-phy
22              - qcom,sm8650-snps-eusb2-phy
23              - qcom,x1e80100-snps-eusb2-phy
24          - const: qcom,sm8550-snps-eusb2-phy
25      - const: qcom,sm8550-snps-eusb2-phy
26
27  reg:
28    maxItems: 1
29
30  "#phy-cells":
31    const: 0
32
33  clocks:
34    items:
35      - description: ref
36
37  clock-names:
38    items:
39      - const: ref
40
41  resets:
42    maxItems: 1
43
44  phys:
45    maxItems: 1
46    description:
47      Phandle to eUSB2 to USB 2.0 repeater
48
49  vdd-supply:
50    description:
51      Phandle to 0.88V regulator supply to PHY digital circuit.
52
53  vdda12-supply:
54    description:
55      Phandle to 1.2V regulator supply to PHY refclk pll block.
56
57required:
58  - compatible
59  - reg
60  - "#phy-cells"
61  - clocks
62  - clock-names
63  - vdd-supply
64  - vdda12-supply
65  - resets
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
72    #include <dt-bindings/clock/qcom,rpmh.h>
73    #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
74
75    usb_1_hsphy: phy@88e3000 {
76        compatible = "qcom,sm8550-snps-eusb2-phy";
77        reg = <0x88e3000 0x154>;
78        #phy-cells = <0>;
79
80        clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
81        clock-names = "ref";
82
83        vdd-supply = <&vreg_l1e_0p88>;
84        vdda12-supply = <&vreg_l3e_1p2>;
85
86        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
87    };
88