xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision e65e175b07bef5974045cc42238de99057669ca7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-usb43dp-phy
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    maxItems: 4
26
27  clock-names:
28    items:
29      - const: aux
30      - const: ref
31      - const: com_aux
32      - const: usb3_pipe
33
34  power-domains:
35    maxItems: 1
36
37  resets:
38    maxItems: 2
39
40  reset-names:
41    items:
42      - const: phy
43      - const: common
44
45  vdda-phy-supply: true
46
47  vdda-pll-supply: true
48
49  "#clock-cells":
50    const: 1
51    description:
52      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
53
54  "#phy-cells":
55    const: 1
56    description:
57      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
58
59required:
60  - compatible
61  - reg
62  - clocks
63  - clock-names
64  - power-domains
65  - resets
66  - reset-names
67  - vdda-phy-supply
68  - vdda-pll-supply
69  - "#clock-cells"
70  - "#phy-cells"
71
72additionalProperties: false
73
74examples:
75  - |
76    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
77
78    phy@88eb000 {
79      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
80      reg = <0x088eb000 0x4000>;
81
82      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
83               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
84               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
85               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
86      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
87
88      power-domains = <&gcc USB30_PRIM_GDSC>;
89
90      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
91               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
92      reset-names = "phy", "common";
93
94      vdda-phy-supply = <&vreg_l9d>;
95      vdda-pll-supply = <&vreg_l4d>;
96
97      #clock-cells = <1>;
98      #phy-cells = <1>;
99    };
100