xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sar2130p-qmp-usb3-dp-phy
20      - qcom,sc7180-qmp-usb3-dp-phy
21      - qcom,sc7280-qmp-usb3-dp-phy
22      - qcom,sc8180x-qmp-usb3-dp-phy
23      - qcom,sc8280xp-qmp-usb43dp-phy
24      - qcom,sdm845-qmp-usb3-dp-phy
25      - qcom,sm6350-qmp-usb3-dp-phy
26      - qcom,sm8150-qmp-usb3-dp-phy
27      - qcom,sm8250-qmp-usb3-dp-phy
28      - qcom,sm8350-qmp-usb3-dp-phy
29      - qcom,sm8450-qmp-usb3-dp-phy
30      - qcom,sm8550-qmp-usb3-dp-phy
31      - qcom,sm8650-qmp-usb3-dp-phy
32      - qcom,sm8750-qmp-usb3-dp-phy
33      - qcom,x1e80100-qmp-usb3-dp-phy
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    minItems: 4
40    maxItems: 5
41
42  clock-names:
43    minItems: 4
44    items:
45      - const: aux
46      - const: ref
47      - const: com_aux
48      - const: usb3_pipe
49      - const: cfg_ahb
50
51  power-domains:
52    maxItems: 1
53
54  resets:
55    maxItems: 2
56
57  reset-names:
58    items:
59      - const: phy
60      - const: common
61
62  vdda-phy-supply: true
63
64  vdda-pll-supply: true
65
66  "#clock-cells":
67    const: 1
68    description:
69      See include/dt-bindings/phy/phy-qcom-qmp.h
70
71  "#phy-cells":
72    const: 1
73    description:
74      See include/dt-bindings/phy/phy-qcom-qmp.h
75
76  mode-switch: true
77  orientation-switch: true
78
79  ports:
80    $ref: /schemas/graph.yaml#/properties/ports
81    properties:
82      port@0:
83        $ref: /schemas/graph.yaml#/properties/port
84        description: Output endpoint of the PHY
85
86      port@1:
87        $ref: /schemas/graph.yaml#/properties/port
88        description: Incoming endpoint from the USB controller
89
90      port@2:
91        $ref: /schemas/graph.yaml#/properties/port
92        description: Incoming endpoint from the DisplayPort controller
93
94required:
95  - compatible
96  - reg
97  - clocks
98  - clock-names
99  - resets
100  - reset-names
101  - vdda-phy-supply
102  - vdda-pll-supply
103  - "#clock-cells"
104  - "#phy-cells"
105
106allOf:
107  - $ref: /schemas/usb/usb-switch.yaml#
108  - if:
109      properties:
110        compatible:
111          enum:
112            - qcom,sc7180-qmp-usb3-dp-phy
113            - qcom,sdm845-qmp-usb3-dp-phy
114    then:
115      properties:
116        clocks:
117          maxItems: 5
118        clock-names:
119          maxItems: 5
120    else:
121      properties:
122        clocks:
123          maxItems: 4
124        clock-names:
125          maxItems: 4
126
127  - if:
128      properties:
129        compatible:
130          enum:
131            - qcom,sar2130p-qmp-usb3-dp-phy
132            - qcom,sc8280xp-qmp-usb43dp-phy
133            - qcom,sm6350-qmp-usb3-dp-phy
134            - qcom,sm8550-qmp-usb3-dp-phy
135            - qcom,sm8650-qmp-usb3-dp-phy
136            - qcom,sm8750-qmp-usb3-dp-phy
137            - qcom,x1e80100-qmp-usb3-dp-phy
138    then:
139      required:
140        - power-domains
141    else:
142      properties:
143        power-domains: false
144
145additionalProperties: false
146
147examples:
148  - |
149    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
150
151    phy@88eb000 {
152      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
153      reg = <0x088eb000 0x4000>;
154
155      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
156               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
157               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
158               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
159      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
160
161      power-domains = <&gcc USB30_PRIM_GDSC>;
162
163      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
164               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
165      reset-names = "phy", "common";
166
167      vdda-phy-supply = <&vreg_l9d>;
168      vdda-pll-supply = <&vreg_l4d>;
169
170      orientation-switch;
171
172      #clock-cells = <1>;
173      #phy-cells = <1>;
174
175      ports {
176          #address-cells = <1>;
177          #size-cells = <0>;
178
179          port@0 {
180              reg = <0>;
181
182              endpoint {
183                  remote-endpoint = <&typec_connector_ss>;
184              };
185          };
186
187          port@1 {
188              reg = <1>;
189
190              endpoint {
191                  remote-endpoint = <&dwc3_ss_out>;
192              };
193          };
194
195          port@2 {
196              reg = <2>;
197
198              endpoint {
199                  remote-endpoint = <&mdss_dp_out>;
200              };
201          };
202      };
203    };
204