xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision 8a922b7728a93d837954315c98b84f6b78de0c4f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-usb43dp-phy
20      - qcom,sm6350-qmp-usb3-dp-phy
21      - qcom,sm8350-qmp-usb3-dp-phy
22      - qcom,sm8450-qmp-usb3-dp-phy
23      - qcom,sm8550-qmp-usb3-dp-phy
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    maxItems: 4
30
31  clock-names:
32    items:
33      - const: aux
34      - const: ref
35      - const: com_aux
36      - const: usb3_pipe
37
38  power-domains:
39    maxItems: 1
40
41  resets:
42    maxItems: 2
43
44  reset-names:
45    items:
46      - const: phy
47      - const: common
48
49  vdda-phy-supply: true
50
51  vdda-pll-supply: true
52
53  "#clock-cells":
54    const: 1
55    description:
56      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
57
58  "#phy-cells":
59    const: 1
60    description:
61      See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
62
63required:
64  - compatible
65  - reg
66  - clocks
67  - clock-names
68  - power-domains
69  - resets
70  - reset-names
71  - vdda-phy-supply
72  - vdda-pll-supply
73  - "#clock-cells"
74  - "#phy-cells"
75
76additionalProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
81
82    phy@88eb000 {
83      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
84      reg = <0x088eb000 0x4000>;
85
86      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
87               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
88               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
89               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
90      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
91
92      power-domains = <&gcc USB30_PRIM_GDSC>;
93
94      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
95               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
96      reset-names = "phy", "common";
97
98      vdda-phy-supply = <&vreg_l9d>;
99      vdda-pll-supply = <&vreg_l4d>;
100
101      #clock-cells = <1>;
102      #phy-cells = <1>;
103    };
104