1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (UFS, SC8280XP) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 The QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - enum: 21 - qcom,qcs615-qmp-ufs-phy 22 - const: qcom,sm6115-qmp-ufs-phy 23 - items: 24 - enum: 25 - qcom,qcs8300-qmp-ufs-phy 26 - const: qcom,sa8775p-qmp-ufs-phy 27 - enum: 28 - qcom,msm8996-qmp-ufs-phy 29 - qcom,msm8998-qmp-ufs-phy 30 - qcom,sa8775p-qmp-ufs-phy 31 - qcom,sc7180-qmp-ufs-phy 32 - qcom,sc7280-qmp-ufs-phy 33 - qcom,sc8180x-qmp-ufs-phy 34 - qcom,sc8280xp-qmp-ufs-phy 35 - qcom,sdm845-qmp-ufs-phy 36 - qcom,sm6115-qmp-ufs-phy 37 - qcom,sm6125-qmp-ufs-phy 38 - qcom,sm6350-qmp-ufs-phy 39 - qcom,sm7150-qmp-ufs-phy 40 - qcom,sm8150-qmp-ufs-phy 41 - qcom,sm8250-qmp-ufs-phy 42 - qcom,sm8350-qmp-ufs-phy 43 - qcom,sm8450-qmp-ufs-phy 44 - qcom,sm8475-qmp-ufs-phy 45 - qcom,sm8550-qmp-ufs-phy 46 - qcom,sm8650-qmp-ufs-phy 47 48 reg: 49 maxItems: 1 50 51 clocks: 52 minItems: 2 53 maxItems: 3 54 55 clock-names: 56 minItems: 2 57 maxItems: 3 58 59 power-domains: 60 maxItems: 1 61 62 resets: 63 maxItems: 1 64 65 reset-names: 66 items: 67 - const: ufsphy 68 69 vdda-phy-supply: true 70 71 vdda-pll-supply: true 72 73 "#clock-cells": 74 const: 1 75 76 "#phy-cells": 77 const: 0 78 79required: 80 - compatible 81 - reg 82 - clocks 83 - clock-names 84 - resets 85 - reset-names 86 - vdda-phy-supply 87 - vdda-pll-supply 88 - "#phy-cells" 89 90allOf: 91 - if: 92 properties: 93 compatible: 94 contains: 95 enum: 96 - qcom,msm8998-qmp-ufs-phy 97 - qcom,sa8775p-qmp-ufs-phy 98 - qcom,sc7180-qmp-ufs-phy 99 - qcom,sc7280-qmp-ufs-phy 100 - qcom,sc8180x-qmp-ufs-phy 101 - qcom,sc8280xp-qmp-ufs-phy 102 - qcom,sdm845-qmp-ufs-phy 103 - qcom,sm6115-qmp-ufs-phy 104 - qcom,sm6125-qmp-ufs-phy 105 - qcom,sm6350-qmp-ufs-phy 106 - qcom,sm7150-qmp-ufs-phy 107 - qcom,sm8150-qmp-ufs-phy 108 - qcom,sm8250-qmp-ufs-phy 109 - qcom,sm8350-qmp-ufs-phy 110 - qcom,sm8450-qmp-ufs-phy 111 - qcom,sm8475-qmp-ufs-phy 112 - qcom,sm8550-qmp-ufs-phy 113 - qcom,sm8650-qmp-ufs-phy 114 then: 115 properties: 116 clocks: 117 minItems: 3 118 maxItems: 3 119 clock-names: 120 items: 121 - const: ref 122 - const: ref_aux 123 - const: qref 124 125 - if: 126 properties: 127 compatible: 128 contains: 129 enum: 130 - qcom,msm8996-qmp-ufs-phy 131 then: 132 properties: 133 clocks: 134 minItems: 2 135 maxItems: 2 136 clock-names: 137 items: 138 - const: ref 139 - const: qref 140 141 - if: 142 properties: 143 compatible: 144 contains: 145 enum: 146 - qcom,msm8996-qmp-ufs-phy 147 - qcom,msm8998-qmp-ufs-phy 148 then: 149 properties: 150 power-domains: 151 false 152 else: 153 required: 154 - power-domains 155 156additionalProperties: false 157 158examples: 159 - | 160 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 161 #include <dt-bindings/clock/qcom,rpmh.h> 162 163 ufs_mem_phy: phy@1d87000 { 164 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 165 reg = <0x01d87000 0x1000>; 166 167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 168 <&gcc GCC_UFS_REF_CLKREF_CLK>; 169 170 clock-names = "ref", "ref_aux", "qref"; 171 172 power-domains = <&gcc UFS_PHY_GDSC>; 173 174 resets = <&ufs_mem_hc 0>; 175 reset-names = "ufsphy"; 176 177 vdda-phy-supply = <&vreg_l6b>; 178 vdda-pll-supply = <&vreg_l3b>; 179 180 #phy-cells = <0>; 181 }; 182