xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision eb01fe7abbe2d0b38824d2a93fdb4cc3eaf2ccc1) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sa8775p-qmp-gen4x2-pcie-phy
20      - qcom,sa8775p-qmp-gen4x4-pcie-phy
21      - qcom,sc8180x-qmp-pcie-phy
22      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25      - qcom,sdm845-qhp-pcie-phy
26      - qcom,sdm845-qmp-pcie-phy
27      - qcom,sdx55-qmp-pcie-phy
28      - qcom,sdx65-qmp-gen4x2-pcie-phy
29      - qcom,sm8150-qmp-gen3x1-pcie-phy
30      - qcom,sm8150-qmp-gen3x2-pcie-phy
31      - qcom,sm8250-qmp-gen3x1-pcie-phy
32      - qcom,sm8250-qmp-gen3x2-pcie-phy
33      - qcom,sm8250-qmp-modem-pcie-phy
34      - qcom,sm8350-qmp-gen3x1-pcie-phy
35      - qcom,sm8450-qmp-gen3x1-pcie-phy
36      - qcom,sm8450-qmp-gen4x2-pcie-phy
37      - qcom,sm8550-qmp-gen3x2-pcie-phy
38      - qcom,sm8550-qmp-gen4x2-pcie-phy
39      - qcom,sm8650-qmp-gen3x2-pcie-phy
40      - qcom,sm8650-qmp-gen4x2-pcie-phy
41      - qcom,x1e80100-qmp-gen3x2-pcie-phy
42      - qcom,x1e80100-qmp-gen4x2-pcie-phy
43
44  reg:
45    minItems: 1
46    maxItems: 2
47
48  clocks:
49    minItems: 5
50    maxItems: 7
51
52  clock-names:
53    minItems: 5
54    items:
55      - const: aux
56      - const: cfg_ahb
57      - const: ref
58      - enum: [rchng, refgen]
59      - const: pipe
60      - const: pipediv2
61      - const: phy_aux
62
63  power-domains:
64    maxItems: 1
65
66  resets:
67    minItems: 1
68    maxItems: 2
69
70  reset-names:
71    minItems: 1
72    items:
73      - const: phy
74      - const: phy_nocsr
75
76  vdda-phy-supply: true
77
78  vdda-pll-supply: true
79
80  vdda-qref-supply: true
81
82  qcom,4ln-config-sel:
83    description: PCIe 4-lane configuration
84    $ref: /schemas/types.yaml#/definitions/phandle-array
85    items:
86      - items:
87          - description: phandle of TCSR syscon
88          - description: offset of PCIe 4-lane configuration register
89          - description: offset of configuration bit for this PHY
90
91  "#clock-cells":
92    const: 0
93
94  clock-output-names:
95    maxItems: 1
96
97  "#phy-cells":
98    const: 0
99
100required:
101  - compatible
102  - reg
103  - clocks
104  - clock-names
105  - resets
106  - reset-names
107  - vdda-phy-supply
108  - vdda-pll-supply
109  - "#clock-cells"
110  - clock-output-names
111  - "#phy-cells"
112
113additionalProperties: false
114
115allOf:
116  - if:
117      properties:
118        compatible:
119          contains:
120            enum:
121              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
122    then:
123      properties:
124        reg:
125          items:
126            - description: port a
127            - description: port b
128      required:
129        - qcom,4ln-config-sel
130    else:
131      properties:
132        reg:
133          maxItems: 1
134
135  - if:
136      properties:
137        compatible:
138          contains:
139            enum:
140              - qcom,sc8180x-qmp-pcie-phy
141              - qcom,sdm845-qhp-pcie-phy
142              - qcom,sdm845-qmp-pcie-phy
143              - qcom,sdx55-qmp-pcie-phy
144              - qcom,sm8150-qmp-gen3x1-pcie-phy
145              - qcom,sm8150-qmp-gen3x2-pcie-phy
146              - qcom,sm8250-qmp-gen3x1-pcie-phy
147              - qcom,sm8250-qmp-gen3x2-pcie-phy
148              - qcom,sm8250-qmp-modem-pcie-phy
149              - qcom,sm8350-qmp-gen3x1-pcie-phy
150              - qcom,sm8450-qmp-gen3x1-pcie-phy
151              - qcom,sm8450-qmp-gen3x2-pcie-phy
152              - qcom,sm8550-qmp-gen3x2-pcie-phy
153              - qcom,sm8550-qmp-gen4x2-pcie-phy
154              - qcom,sm8650-qmp-gen3x2-pcie-phy
155              - qcom,sm8650-qmp-gen4x2-pcie-phy
156              - qcom,x1e80100-qmp-gen3x2-pcie-phy
157              - qcom,x1e80100-qmp-gen4x2-pcie-phy
158    then:
159      properties:
160        clocks:
161          maxItems: 5
162        clock-names:
163          maxItems: 5
164
165  - if:
166      properties:
167        compatible:
168          contains:
169            enum:
170              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
171              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
172              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
173    then:
174      properties:
175        clocks:
176          minItems: 6
177        clock-names:
178          minItems: 6
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - qcom,sa8775p-qmp-gen4x2-pcie-phy
186              - qcom,sa8775p-qmp-gen4x4-pcie-phy
187    then:
188      properties:
189        clocks:
190          minItems: 7
191        clock-names:
192          minItems: 7
193
194  - if:
195      properties:
196        compatible:
197          contains:
198            enum:
199              - qcom,sm8550-qmp-gen4x2-pcie-phy
200              - qcom,sm8650-qmp-gen4x2-pcie-phy
201              - qcom,x1e80100-qmp-gen3x2-pcie-phy
202              - qcom,x1e80100-qmp-gen4x2-pcie-phy
203    then:
204      properties:
205        resets:
206          minItems: 2
207        reset-names:
208          minItems: 2
209    else:
210      properties:
211        resets:
212          maxItems: 1
213        reset-names:
214          maxItems: 1
215
216examples:
217  - |
218    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
219
220    pcie2b_phy: phy@1c18000 {
221      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
222      reg = <0x01c18000 0x2000>;
223
224      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
225               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
226               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
227               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
228               <&gcc GCC_PCIE_2B_PIPE_CLK>,
229               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
230      clock-names = "aux", "cfg_ahb", "ref", "rchng",
231                    "pipe", "pipediv2";
232
233      power-domains = <&gcc PCIE_2B_GDSC>;
234
235      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
236      reset-names = "phy";
237
238      vdda-phy-supply = <&vreg_l6d>;
239      vdda-pll-supply = <&vreg_l4d>;
240
241      #clock-cells = <0>;
242      clock-output-names = "pcie_2b_pipe_clk";
243
244      #phy-cells = <0>;
245    };
246
247    pcie2a_phy: phy@1c24000 {
248      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
249      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
250
251      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
252               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
253               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
254               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
255               <&gcc GCC_PCIE_2A_PIPE_CLK>,
256               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
257      clock-names = "aux", "cfg_ahb", "ref", "rchng",
258                    "pipe", "pipediv2";
259
260      power-domains = <&gcc PCIE_2A_GDSC>;
261
262      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
263      reset-names = "phy";
264
265      vdda-phy-supply = <&vreg_l6d>;
266      vdda-pll-supply = <&vreg_l4d>;
267
268      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
269
270      #clock-cells = <0>;
271      clock-output-names = "pcie_2a_pipe_clk";
272
273      #phy-cells = <0>;
274    };
275