xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sa8775p-qmp-gen4x2-pcie-phy
20      - qcom,sa8775p-qmp-gen4x4-pcie-phy
21      - qcom,sc8180x-qmp-pcie-phy
22      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25      - qcom,sdm845-qhp-pcie-phy
26      - qcom,sdm845-qmp-pcie-phy
27      - qcom,sdx55-qmp-pcie-phy
28      - qcom,sdx65-qmp-gen4x2-pcie-phy
29      - qcom,sm8150-qmp-gen3x1-pcie-phy
30      - qcom,sm8150-qmp-gen3x2-pcie-phy
31      - qcom,sm8250-qmp-gen3x1-pcie-phy
32      - qcom,sm8250-qmp-gen3x2-pcie-phy
33      - qcom,sm8250-qmp-modem-pcie-phy
34      - qcom,sm8350-qmp-gen3x1-pcie-phy
35      - qcom,sm8450-qmp-gen3x1-pcie-phy
36      - qcom,sm8450-qmp-gen4x2-pcie-phy
37      - qcom,sm8550-qmp-gen3x2-pcie-phy
38      - qcom,sm8550-qmp-gen4x2-pcie-phy
39      - qcom,sm8650-qmp-gen3x2-pcie-phy
40      - qcom,sm8650-qmp-gen4x2-pcie-phy
41      - qcom,x1e80100-qmp-gen3x2-pcie-phy
42      - qcom,x1e80100-qmp-gen4x2-pcie-phy
43      - qcom,x1e80100-qmp-gen4x4-pcie-phy
44      - qcom,x1e80100-qmp-gen4x8-pcie-phy
45
46  reg:
47    minItems: 1
48    maxItems: 2
49
50  clocks:
51    minItems: 5
52    maxItems: 7
53
54  clock-names:
55    minItems: 5
56    items:
57      - const: aux
58      - const: cfg_ahb
59      - const: ref
60      - enum: [rchng, refgen]
61      - const: pipe
62      - const: pipediv2
63      - const: phy_aux
64
65  power-domains:
66    maxItems: 1
67
68  resets:
69    minItems: 1
70    maxItems: 2
71
72  reset-names:
73    minItems: 1
74    items:
75      - const: phy
76      - const: phy_nocsr
77
78  vdda-phy-supply: true
79
80  vdda-pll-supply: true
81
82  vdda-qref-supply: true
83
84  qcom,4ln-config-sel:
85    description: PCIe 4-lane configuration
86    $ref: /schemas/types.yaml#/definitions/phandle-array
87    items:
88      - items:
89          - description: phandle of TCSR syscon
90          - description: offset of PCIe 4-lane configuration register
91          - description: offset of configuration bit for this PHY
92
93  "#clock-cells": true
94
95  clock-output-names:
96    maxItems: 1
97
98  "#phy-cells":
99    const: 0
100
101required:
102  - compatible
103  - reg
104  - clocks
105  - clock-names
106  - resets
107  - reset-names
108  - vdda-phy-supply
109  - vdda-pll-supply
110  - "#clock-cells"
111  - clock-output-names
112  - "#phy-cells"
113
114additionalProperties: false
115
116allOf:
117  - if:
118      properties:
119        compatible:
120          contains:
121            enum:
122              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
123              - qcom,x1e80100-qmp-gen4x4-pcie-phy
124    then:
125      properties:
126        reg:
127          items:
128            - description: port a
129            - description: port b
130      required:
131        - qcom,4ln-config-sel
132    else:
133      properties:
134        reg:
135          maxItems: 1
136
137  - if:
138      properties:
139        compatible:
140          contains:
141            enum:
142              - qcom,sc8180x-qmp-pcie-phy
143              - qcom,sdm845-qhp-pcie-phy
144              - qcom,sdm845-qmp-pcie-phy
145              - qcom,sdx55-qmp-pcie-phy
146              - qcom,sm8150-qmp-gen3x1-pcie-phy
147              - qcom,sm8150-qmp-gen3x2-pcie-phy
148              - qcom,sm8250-qmp-gen3x1-pcie-phy
149              - qcom,sm8250-qmp-gen3x2-pcie-phy
150              - qcom,sm8250-qmp-modem-pcie-phy
151              - qcom,sm8350-qmp-gen3x1-pcie-phy
152              - qcom,sm8450-qmp-gen3x1-pcie-phy
153              - qcom,sm8450-qmp-gen3x2-pcie-phy
154              - qcom,sm8550-qmp-gen3x2-pcie-phy
155              - qcom,sm8550-qmp-gen4x2-pcie-phy
156              - qcom,sm8650-qmp-gen3x2-pcie-phy
157              - qcom,sm8650-qmp-gen4x2-pcie-phy
158    then:
159      properties:
160        clocks:
161          maxItems: 5
162        clock-names:
163          maxItems: 5
164
165  - if:
166      properties:
167        compatible:
168          contains:
169            enum:
170              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
171              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
172              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
173              - qcom,x1e80100-qmp-gen3x2-pcie-phy
174              - qcom,x1e80100-qmp-gen4x2-pcie-phy
175              - qcom,x1e80100-qmp-gen4x4-pcie-phy
176              - qcom,x1e80100-qmp-gen4x8-pcie-phy
177    then:
178      properties:
179        clocks:
180          minItems: 6
181        clock-names:
182          minItems: 6
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - qcom,sa8775p-qmp-gen4x2-pcie-phy
190              - qcom,sa8775p-qmp-gen4x4-pcie-phy
191    then:
192      properties:
193        clocks:
194          minItems: 7
195        clock-names:
196          minItems: 7
197
198  - if:
199      properties:
200        compatible:
201          contains:
202            enum:
203              - qcom,sm8550-qmp-gen4x2-pcie-phy
204              - qcom,sm8650-qmp-gen4x2-pcie-phy
205              - qcom,x1e80100-qmp-gen4x2-pcie-phy
206              - qcom,x1e80100-qmp-gen4x4-pcie-phy
207              - qcom,x1e80100-qmp-gen4x8-pcie-phy
208    then:
209      properties:
210        resets:
211          minItems: 2
212        reset-names:
213          minItems: 2
214    else:
215      properties:
216        resets:
217          maxItems: 1
218        reset-names:
219          maxItems: 1
220
221  - if:
222      properties:
223        compatible:
224          contains:
225            enum:
226              - qcom,sm8450-qmp-gen4x2-pcie-phy
227              - qcom,sm8550-qmp-gen4x2-pcie-phy
228              - qcom,sm8650-qmp-gen4x2-pcie-phy
229    then:
230      properties:
231        "#clock-cells":
232          const: 1
233    else:
234      properties:
235        "#clock-cells":
236          const: 0
237
238examples:
239  - |
240    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
241
242    pcie2b_phy: phy@1c18000 {
243      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
244      reg = <0x01c18000 0x2000>;
245
246      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
247               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
248               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
249               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
250               <&gcc GCC_PCIE_2B_PIPE_CLK>,
251               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
252      clock-names = "aux", "cfg_ahb", "ref", "rchng",
253                    "pipe", "pipediv2";
254
255      power-domains = <&gcc PCIE_2B_GDSC>;
256
257      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
258      reset-names = "phy";
259
260      vdda-phy-supply = <&vreg_l6d>;
261      vdda-pll-supply = <&vreg_l4d>;
262
263      #clock-cells = <0>;
264      clock-output-names = "pcie_2b_pipe_clk";
265
266      #phy-cells = <0>;
267    };
268
269    pcie2a_phy: phy@1c24000 {
270      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
271      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
272
273      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
274               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
275               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
276               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
277               <&gcc GCC_PCIE_2A_PIPE_CLK>,
278               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
279      clock-names = "aux", "cfg_ahb", "ref", "rchng",
280                    "pipe", "pipediv2";
281
282      power-domains = <&gcc PCIE_2A_GDSC>;
283
284      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
285      reset-names = "phy";
286
287      vdda-phy-supply = <&vreg_l6d>;
288      vdda-pll-supply = <&vreg_l4d>;
289
290      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
291
292      #clock-cells = <0>;
293      clock-output-names = "pcie_2a_pipe_clk";
294
295      #phy-cells = <0>;
296    };
297