xref: /linux/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq6018-qusb2-phy
22              - qcom,ipq8074-qusb2-phy
23              - qcom,ipq9574-qusb2-phy
24              - qcom,msm8953-qusb2-phy
25              - qcom,msm8996-qusb2-phy
26              - qcom,msm8998-qusb2-phy
27              - qcom,qcm2290-qusb2-phy
28              - qcom,qcs615-qusb2-phy
29              - qcom,sdm660-qusb2-phy
30              - qcom,sm4250-qusb2-phy
31              - qcom,sm6115-qusb2-phy
32      - items:
33          - enum:
34              - qcom,sc7180-qusb2-phy
35              - qcom,sdm670-qusb2-phy
36              - qcom,sdm845-qusb2-phy
37              - qcom,sm6350-qusb2-phy
38          - const: qcom,qusb2-v2-phy
39  reg:
40    maxItems: 1
41
42  "#phy-cells":
43    const: 0
44
45  clocks:
46    minItems: 2
47    items:
48      - description: phy config clock
49      - description: 19.2 MHz ref clk
50      - description: phy interface clock (Optional)
51
52  clock-names:
53    minItems: 2
54    items:
55      - const: cfg_ahb
56      - const: ref
57      - const: iface
58
59  vdd-supply:
60    description:
61      Phandle to 0.9V regulator supply to PHY digital circuit.
62
63  vdda-pll-supply:
64    description:
65      Phandle to 1.8V regulator supply to PHY refclk pll block.
66
67  vdda-phy-dpdm-supply:
68    description:
69      Phandle to 3.1V regulator supply to Dp/Dm port signals.
70
71  resets:
72    maxItems: 1
73    description:
74      Phandle to reset to phy block.
75
76  nvmem-cells:
77    maxItems: 1
78    description:
79      Phandle to nvmem cell that contains 'HS Tx trim'
80      tuning parameter value for qusb2 phy.
81
82  qcom,tcsr-syscon:
83    description:
84      Phandle to TCSR syscon register region.
85    $ref: /schemas/types.yaml#/definitions/phandle
86
87  qcom,imp-res-offset-value:
88    description:
89      It is a 6 bit value that specifies offset to be
90      added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
91      tuning parameter that may vary for different boards of same SOC.
92    $ref: /schemas/types.yaml#/definitions/uint32
93    minimum: 0
94    maximum: 63
95    default: 0
96
97  qcom,bias-ctrl-value:
98    description:
99      It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
100      tuning parameter that may vary for different boards of same SOC.
101    $ref: /schemas/types.yaml#/definitions/uint32
102    minimum: 0
103    maximum: 63
104    default: 32
105
106  qcom,charge-ctrl-value:
107    description:
108      It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
109      tuning parameter that may vary for different boards of same SOC.
110    $ref: /schemas/types.yaml#/definitions/uint32
111    minimum: 0
112    maximum: 3
113    default: 0
114
115  qcom,hstx-trim-value:
116    description:
117      It is a 4 bit value that specifies tuning for HSTX
118      output current.
119      Possible range is - 15mA to 24mA (stepsize of 600 uA).
120      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
121    $ref: /schemas/types.yaml#/definitions/uint32
122    minimum: 0
123    maximum: 15
124    default: 3
125
126  qcom,preemphasis-level:
127    description:
128      It is a 2 bit value that specifies pre-emphasis level.
129      Possible range is 0 to 15% (stepsize of 5%).
130      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
131    $ref: /schemas/types.yaml#/definitions/uint32
132    minimum: 0
133    maximum: 3
134    default: 2
135
136  qcom,preemphasis-width:
137    description:
138      It is a 1 bit value that specifies how long the HSTX
139      pre-emphasis (specified using qcom,preemphasis-level) must be in
140      effect. Duration could be half-bit of full-bit.
141      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
142    $ref: /schemas/types.yaml#/definitions/uint32
143    minimum: 0
144    maximum: 1
145    default: 0
146
147  qcom,hsdisc-trim-value:
148    description:
149      It is a 2 bit value tuning parameter that control disconnect
150      threshold and may vary for different boards of same SOC.
151    $ref: /schemas/types.yaml#/definitions/uint32
152    minimum: 0
153    maximum: 3
154    default: 0
155
156required:
157  - compatible
158  - reg
159  - "#phy-cells"
160  - clocks
161  - clock-names
162  - vdd-supply
163  - vdda-pll-supply
164  - vdda-phy-dpdm-supply
165  - resets
166
167allOf:
168  - if:
169      not:
170        properties:
171          compatible:
172            contains:
173              const: qcom,qusb2-v2-phy
174    then:
175      properties:
176        qcom,imp-res-offset-value: false
177        qcom,bias-ctrl-value: false
178        qcom,charge-ctrl-value: false
179        qcom,hstx-trim-value: false
180        qcom,preemphasis-level: false
181        qcom,preemphasis-width: false
182        qcom,hsdisc-trim-value: false
183
184additionalProperties: false
185
186examples:
187  - |
188    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
189    hsusb_phy: phy@7411000 {
190        compatible = "qcom,msm8996-qusb2-phy";
191        reg = <0x7411000 0x180>;
192        #phy-cells = <0>;
193
194        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
195                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
196        clock-names = "cfg_ahb", "ref";
197
198        vdd-supply = <&pm8994_l28>;
199        vdda-pll-supply = <&pm8994_l12>;
200        vdda-phy-dpdm-supply = <&pm8994_l24>;
201
202        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
203        nvmem-cells = <&qusb2p_hstx_trim>;
204    };
205