xref: /linux/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq5424-qusb2-phy
22              - qcom,ipq6018-qusb2-phy
23              - qcom,ipq8074-qusb2-phy
24              - qcom,ipq9574-qusb2-phy
25              - qcom,msm8953-qusb2-phy
26              - qcom,msm8996-qusb2-phy
27              - qcom,msm8998-qusb2-phy
28              - qcom,qcm2290-qusb2-phy
29              - qcom,qcs615-qusb2-phy
30              - qcom,sdm660-qusb2-phy
31              - qcom,shikra-qusb2-phy
32              - qcom,sm4250-qusb2-phy
33              - qcom,sm6115-qusb2-phy
34      - items:
35          - enum:
36              - qcom,ipq5210-qusb2-phy
37          - const: qcom,ipq6018-qusb2-phy
38      - items:
39          - enum:
40              - qcom,sc7180-qusb2-phy
41              - qcom,sdm670-qusb2-phy
42              - qcom,sdm845-qusb2-phy
43              - qcom,sm6350-qusb2-phy
44          - const: qcom,qusb2-v2-phy
45  reg:
46    maxItems: 1
47
48  "#phy-cells":
49    const: 0
50
51  clocks:
52    minItems: 2
53    items:
54      - description: phy config clock
55      - description: 19.2 MHz ref clk
56      - description: phy interface clock (Optional)
57
58  clock-names:
59    minItems: 2
60    items:
61      - const: cfg_ahb
62      - const: ref
63      - const: iface
64
65  vdd-supply:
66    description:
67      Phandle to 0.9V regulator supply to PHY digital circuit.
68
69  vdda-pll-supply:
70    description:
71      Phandle to 1.8V regulator supply to PHY refclk pll block.
72
73  vdda-phy-dpdm-supply:
74    description:
75      Phandle to 3.1V regulator supply to Dp/Dm port signals.
76
77  resets:
78    maxItems: 1
79    description:
80      Phandle to reset to phy block.
81
82  nvmem-cells:
83    maxItems: 1
84    description:
85      Phandle to nvmem cell that contains 'HS Tx trim'
86      tuning parameter value for qusb2 phy.
87
88  qcom,tcsr-syscon:
89    description:
90      Phandle to TCSR syscon register region.
91    $ref: /schemas/types.yaml#/definitions/phandle
92
93  qcom,imp-res-offset-value:
94    description:
95      It is a 6 bit value that specifies offset to be
96      added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
97      tuning parameter that may vary for different boards of same SOC.
98    $ref: /schemas/types.yaml#/definitions/uint32
99    minimum: 0
100    maximum: 63
101    default: 0
102
103  qcom,bias-ctrl-value:
104    description:
105      It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
106      tuning parameter that may vary for different boards of same SOC.
107    $ref: /schemas/types.yaml#/definitions/uint32
108    minimum: 0
109    maximum: 63
110    default: 32
111
112  qcom,charge-ctrl-value:
113    description:
114      It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
115      tuning parameter that may vary for different boards of same SOC.
116    $ref: /schemas/types.yaml#/definitions/uint32
117    minimum: 0
118    maximum: 3
119    default: 0
120
121  qcom,hstx-trim-value:
122    description:
123      It is a 4 bit value that specifies tuning for HSTX
124      output current.
125      Possible range is - 15mA to 24mA (stepsize of 600 uA).
126      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
127    $ref: /schemas/types.yaml#/definitions/uint32
128    minimum: 0
129    maximum: 15
130    default: 3
131
132  qcom,preemphasis-level:
133    description:
134      It is a 2 bit value that specifies pre-emphasis level.
135      Possible range is 0 to 15% (stepsize of 5%).
136      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
137    $ref: /schemas/types.yaml#/definitions/uint32
138    minimum: 0
139    maximum: 3
140    default: 2
141
142  qcom,preemphasis-width:
143    description:
144      It is a 1 bit value that specifies how long the HSTX
145      pre-emphasis (specified using qcom,preemphasis-level) must be in
146      effect. Duration could be half-bit of full-bit.
147      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
148    $ref: /schemas/types.yaml#/definitions/uint32
149    minimum: 0
150    maximum: 1
151    default: 0
152
153  qcom,hsdisc-trim-value:
154    description:
155      It is a 2 bit value tuning parameter that control disconnect
156      threshold and may vary for different boards of same SOC.
157    $ref: /schemas/types.yaml#/definitions/uint32
158    minimum: 0
159    maximum: 3
160    default: 0
161
162required:
163  - compatible
164  - reg
165  - "#phy-cells"
166  - clocks
167  - clock-names
168  - vdd-supply
169  - vdda-pll-supply
170  - vdda-phy-dpdm-supply
171  - resets
172
173allOf:
174  - if:
175      not:
176        properties:
177          compatible:
178            contains:
179              const: qcom,qusb2-v2-phy
180    then:
181      properties:
182        qcom,imp-res-offset-value: false
183        qcom,bias-ctrl-value: false
184        qcom,charge-ctrl-value: false
185        qcom,hstx-trim-value: false
186        qcom,preemphasis-level: false
187        qcom,preemphasis-width: false
188        qcom,hsdisc-trim-value: false
189
190additionalProperties: false
191
192examples:
193  - |
194    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
195    hsusb_phy: phy@7411000 {
196        compatible = "qcom,msm8996-qusb2-phy";
197        reg = <0x7411000 0x180>;
198        #phy-cells = <0>;
199
200        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
201                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
202        clock-names = "cfg_ahb", "ref";
203
204        vdd-supply = <&pm8994_l28>;
205        vdda-pll-supply = <&pm8994_l12>;
206        vdda-phy-dpdm-supply = <&pm8994_l24>;
207
208        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
209        nvmem-cells = <&qusb2p_hstx_trim>;
210    };
211