xref: /linux/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml (revision 05d32474ab547fb097cfe3f3eb00a2aa7cdf4067) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Wesley Cheng <quic_wcheng@quicinc.com>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq5424-qusb2-phy
22              - qcom,ipq6018-qusb2-phy
23              - qcom,ipq8074-qusb2-phy
24              - qcom,ipq9574-qusb2-phy
25              - qcom,msm8953-qusb2-phy
26              - qcom,msm8996-qusb2-phy
27              - qcom,msm8998-qusb2-phy
28              - qcom,qcm2290-qusb2-phy
29              - qcom,qcs615-qusb2-phy
30              - qcom,sdm660-qusb2-phy
31              - qcom,sm4250-qusb2-phy
32              - qcom,sm6115-qusb2-phy
33      - items:
34          - enum:
35              - qcom,ipq5210-qusb2-phy
36          - const: qcom,ipq6018-qusb2-phy
37      - items:
38          - enum:
39              - qcom,sc7180-qusb2-phy
40              - qcom,sdm670-qusb2-phy
41              - qcom,sdm845-qusb2-phy
42              - qcom,sm6350-qusb2-phy
43          - const: qcom,qusb2-v2-phy
44  reg:
45    maxItems: 1
46
47  "#phy-cells":
48    const: 0
49
50  clocks:
51    minItems: 2
52    items:
53      - description: phy config clock
54      - description: 19.2 MHz ref clk
55      - description: phy interface clock (Optional)
56
57  clock-names:
58    minItems: 2
59    items:
60      - const: cfg_ahb
61      - const: ref
62      - const: iface
63
64  vdd-supply:
65    description:
66      Phandle to 0.9V regulator supply to PHY digital circuit.
67
68  vdda-pll-supply:
69    description:
70      Phandle to 1.8V regulator supply to PHY refclk pll block.
71
72  vdda-phy-dpdm-supply:
73    description:
74      Phandle to 3.1V regulator supply to Dp/Dm port signals.
75
76  resets:
77    maxItems: 1
78    description:
79      Phandle to reset to phy block.
80
81  nvmem-cells:
82    maxItems: 1
83    description:
84      Phandle to nvmem cell that contains 'HS Tx trim'
85      tuning parameter value for qusb2 phy.
86
87  qcom,tcsr-syscon:
88    description:
89      Phandle to TCSR syscon register region.
90    $ref: /schemas/types.yaml#/definitions/phandle
91
92  qcom,imp-res-offset-value:
93    description:
94      It is a 6 bit value that specifies offset to be
95      added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
96      tuning parameter that may vary for different boards of same SOC.
97    $ref: /schemas/types.yaml#/definitions/uint32
98    minimum: 0
99    maximum: 63
100    default: 0
101
102  qcom,bias-ctrl-value:
103    description:
104      It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
105      tuning parameter that may vary for different boards of same SOC.
106    $ref: /schemas/types.yaml#/definitions/uint32
107    minimum: 0
108    maximum: 63
109    default: 32
110
111  qcom,charge-ctrl-value:
112    description:
113      It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
114      tuning parameter that may vary for different boards of same SOC.
115    $ref: /schemas/types.yaml#/definitions/uint32
116    minimum: 0
117    maximum: 3
118    default: 0
119
120  qcom,hstx-trim-value:
121    description:
122      It is a 4 bit value that specifies tuning for HSTX
123      output current.
124      Possible range is - 15mA to 24mA (stepsize of 600 uA).
125      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126    $ref: /schemas/types.yaml#/definitions/uint32
127    minimum: 0
128    maximum: 15
129    default: 3
130
131  qcom,preemphasis-level:
132    description:
133      It is a 2 bit value that specifies pre-emphasis level.
134      Possible range is 0 to 15% (stepsize of 5%).
135      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
136    $ref: /schemas/types.yaml#/definitions/uint32
137    minimum: 0
138    maximum: 3
139    default: 2
140
141  qcom,preemphasis-width:
142    description:
143      It is a 1 bit value that specifies how long the HSTX
144      pre-emphasis (specified using qcom,preemphasis-level) must be in
145      effect. Duration could be half-bit of full-bit.
146      See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
147    $ref: /schemas/types.yaml#/definitions/uint32
148    minimum: 0
149    maximum: 1
150    default: 0
151
152  qcom,hsdisc-trim-value:
153    description:
154      It is a 2 bit value tuning parameter that control disconnect
155      threshold and may vary for different boards of same SOC.
156    $ref: /schemas/types.yaml#/definitions/uint32
157    minimum: 0
158    maximum: 3
159    default: 0
160
161required:
162  - compatible
163  - reg
164  - "#phy-cells"
165  - clocks
166  - clock-names
167  - vdd-supply
168  - vdda-pll-supply
169  - vdda-phy-dpdm-supply
170  - resets
171
172allOf:
173  - if:
174      not:
175        properties:
176          compatible:
177            contains:
178              const: qcom,qusb2-v2-phy
179    then:
180      properties:
181        qcom,imp-res-offset-value: false
182        qcom,bias-ctrl-value: false
183        qcom,charge-ctrl-value: false
184        qcom,hstx-trim-value: false
185        qcom,preemphasis-level: false
186        qcom,preemphasis-width: false
187        qcom,hsdisc-trim-value: false
188
189additionalProperties: false
190
191examples:
192  - |
193    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
194    hsusb_phy: phy@7411000 {
195        compatible = "qcom,msm8996-qusb2-phy";
196        reg = <0x7411000 0x180>;
197        #phy-cells = <0>;
198
199        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
200                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
201        clock-names = "cfg_ahb", "ref";
202
203        vdd-supply = <&pm8994_l28>;
204        vdda-pll-supply = <&pm8994_l12>;
205        vdda-phy-dpdm-supply = <&pm8994_l24>;
206
207        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
208        nvmem-cells = <&qusb2p_hstx_trim>;
209    };
210