xref: /linux/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml (revision 8582976acc8504cec53a7b6fed493435eba8437f)
1*1166a2caSWesley Cheng# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*1166a2caSWesley Cheng%YAML 1.2
3*1166a2caSWesley Cheng---
4*1166a2caSWesley Cheng$id: http://devicetree.org/schemas/phy/qcom,m31-eusb2-phy.yaml#
5*1166a2caSWesley Cheng$schema: http://devicetree.org/meta-schemas/core.yaml#
6*1166a2caSWesley Cheng
7*1166a2caSWesley Chengtitle: Qualcomm M31 eUSB2 phy
8*1166a2caSWesley Cheng
9*1166a2caSWesley Chengmaintainers:
10*1166a2caSWesley Cheng  - Wesley Cheng <quic_wcheng@quicinc.com>
11*1166a2caSWesley Cheng
12*1166a2caSWesley Chengdescription:
13*1166a2caSWesley Cheng  M31 based eUSB2 controller, which supports LS/FS/HS usb connectivity
14*1166a2caSWesley Cheng  on Qualcomm chipsets.  It is paired with a eUSB2 repeater.
15*1166a2caSWesley Cheng
16*1166a2caSWesley Chengproperties:
17*1166a2caSWesley Cheng  compatible:
18*1166a2caSWesley Cheng    items:
19*1166a2caSWesley Cheng      - enum:
20*1166a2caSWesley Cheng          - qcom,sm8750-m31-eusb2-phy
21*1166a2caSWesley Cheng
22*1166a2caSWesley Cheng  reg:
23*1166a2caSWesley Cheng    maxItems: 1
24*1166a2caSWesley Cheng
25*1166a2caSWesley Cheng  "#phy-cells":
26*1166a2caSWesley Cheng    const: 0
27*1166a2caSWesley Cheng
28*1166a2caSWesley Cheng  clocks:
29*1166a2caSWesley Cheng    items:
30*1166a2caSWesley Cheng      - description: reference clock
31*1166a2caSWesley Cheng
32*1166a2caSWesley Cheng  clock-names:
33*1166a2caSWesley Cheng    items:
34*1166a2caSWesley Cheng      - const: ref
35*1166a2caSWesley Cheng
36*1166a2caSWesley Cheng  resets:
37*1166a2caSWesley Cheng    maxItems: 1
38*1166a2caSWesley Cheng
39*1166a2caSWesley Cheng  phys:
40*1166a2caSWesley Cheng    maxItems: 1
41*1166a2caSWesley Cheng    description:
42*1166a2caSWesley Cheng      Phandle to eUSB2 repeater
43*1166a2caSWesley Cheng
44*1166a2caSWesley Cheng  vdd-supply:
45*1166a2caSWesley Cheng    description:
46*1166a2caSWesley Cheng      Phandle to 0.88V regulator supply to PHY digital circuit.
47*1166a2caSWesley Cheng
48*1166a2caSWesley Cheng  vdda12-supply:
49*1166a2caSWesley Cheng    description:
50*1166a2caSWesley Cheng      Phandle to 1.2V regulator supply to PHY refclk pll block.
51*1166a2caSWesley Cheng
52*1166a2caSWesley Chengrequired:
53*1166a2caSWesley Cheng  - compatible
54*1166a2caSWesley Cheng  - reg
55*1166a2caSWesley Cheng  - "#phy-cells"
56*1166a2caSWesley Cheng  - clocks
57*1166a2caSWesley Cheng  - clock-names
58*1166a2caSWesley Cheng  - resets
59*1166a2caSWesley Cheng  - vdd-supply
60*1166a2caSWesley Cheng  - vdda12-supply
61*1166a2caSWesley Cheng
62*1166a2caSWesley ChengadditionalProperties: false
63*1166a2caSWesley Cheng
64*1166a2caSWesley Chengexamples:
65*1166a2caSWesley Cheng  - |
66*1166a2caSWesley Cheng    usb_1_hsphy: phy@88e3000 {
67*1166a2caSWesley Cheng        compatible = "qcom,sm8750-m31-eusb2-phy";
68*1166a2caSWesley Cheng        reg = <0x88e3000 0x29c>;
69*1166a2caSWesley Cheng
70*1166a2caSWesley Cheng        clocks = <&tcsrcc_usb2_clkref_en>;
71*1166a2caSWesley Cheng        clock-names = "ref";
72*1166a2caSWesley Cheng
73*1166a2caSWesley Cheng        resets = <&gcc_qusb2phy_prim_bcr>;
74*1166a2caSWesley Cheng
75*1166a2caSWesley Cheng        #phy-cells = <0>;
76*1166a2caSWesley Cheng
77*1166a2caSWesley Cheng        vdd-supply = <&vreg_l2d_0p88>;
78*1166a2caSWesley Cheng        vdda12-supply = <&vreg_l3g_1p2>;
79*1166a2caSWesley Cheng    };
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