1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Qualcomm Adreno/Snapdragon QMP HDMI phy 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13properties: 14 compatible: 15 enum: 16 - qcom,hdmi-phy-8996 17 - qcom,hdmi-phy-8998 18 19 reg: 20 maxItems: 6 21 22 reg-names: 23 items: 24 - const: hdmi_pll 25 - const: hdmi_tx_l0 26 - const: hdmi_tx_l1 27 - const: hdmi_tx_l2 28 - const: hdmi_tx_l3 29 - const: hdmi_phy 30 31 clocks: 32 minItems: 2 33 maxItems: 3 34 35 clock-names: 36 minItems: 2 37 items: 38 - const: iface 39 - const: ref 40 - const: xo 41 42 power-domains: 43 maxItems: 1 44 45 vcca-supply: 46 description: phandle to VCCA supply regulator 47 48 vddio-supply: 49 description: phandle to VDD I/O supply regulator 50 51 '#clock-cells': 52 const: 0 53 54 '#phy-cells': 55 const: 0 56 57required: 58 - compatible 59 - clocks 60 - clock-names 61 - reg 62 - reg-names 63 - '#phy-cells' 64 65additionalProperties: false 66 67examples: 68 - | 69 hdmi-phy@9a0600 { 70 compatible = "qcom,hdmi-phy-8996"; 71 reg = <0x009a0600 0x1c4>, 72 <0x009a0a00 0x124>, 73 <0x009a0c00 0x124>, 74 <0x009a0e00 0x124>, 75 <0x009a1000 0x124>, 76 <0x009a1200 0x0c8>; 77 reg-names = "hdmi_pll", 78 "hdmi_tx_l0", 79 "hdmi_tx_l1", 80 "hdmi_tx_l2", 81 "hdmi_tx_l3", 82 "hdmi_phy"; 83 84 clocks = <&mmcc 116>, 85 <&gcc 214>, 86 <&xo_board>; 87 clock-names = "iface", 88 "ref", 89 "xo"; 90 #clock-cells = <0>; 91 #phy-cells = <0>; 92 93 vddio-supply = <&vreg_l12a_1p8>; 94 vcca-supply = <&vreg_l28a_0p925>; 95 }; 96