xref: /linux/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-7nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 7nm PHY
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12allOf:
13  - $ref: qcom,dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,dsi-phy-7nm
21              - qcom,dsi-phy-7nm-8150
22              - qcom,kaanapali-dsi-phy-3nm
23              - qcom,sa8775p-dsi-phy-5nm
24              - qcom,sar2130p-dsi-phy-5nm
25              - qcom,sc7280-dsi-phy-7nm
26              - qcom,sm6375-dsi-phy-7nm
27              - qcom,sm8350-dsi-phy-5nm
28              - qcom,sm8450-dsi-phy-5nm
29              - qcom,sm8550-dsi-phy-4nm
30              - qcom,sm8650-dsi-phy-4nm
31              - qcom,sm8750-dsi-phy-3nm
32      - items:
33          - enum:
34              - qcom,eliza-dsi-phy-4nm
35          - const: qcom,sm8650-dsi-phy-4nm
36      - items:
37          - enum:
38              - qcom,qcs8300-dsi-phy-5nm
39              - qcom,sc8280xp-dsi-phy-5nm
40          - const: qcom,sa8775p-dsi-phy-5nm
41
42  reg:
43    items:
44      - description: dsi phy register set
45      - description: dsi phy lane register set
46      - description: dsi pll register set
47
48  reg-names:
49    items:
50      - const: dsi_phy
51      - const: dsi_phy_lane
52      - const: dsi_pll
53
54  vdds-supply:
55    description: |
56      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
57
58  phy-type:
59    description: D-PHY (default) or C-PHY mode
60    enum: [ 10, 11 ]
61    default: 10
62
63required:
64  - compatible
65  - reg
66  - reg-names
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
73    #include <dt-bindings/clock/qcom,rpmh.h>
74
75    dsi-phy@ae94400 {
76        compatible = "qcom,dsi-phy-7nm";
77        reg = <0x0ae94400 0x200>,
78              <0x0ae94600 0x280>,
79              <0x0ae94900 0x260>;
80        reg-names = "dsi_phy",
81                    "dsi_phy_lane",
82                    "dsi_pll";
83
84        #clock-cells = <1>;
85        #phy-cells = <0>;
86
87        vdds-supply = <&vreg_l5a_0p88>;
88        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
89                 <&rpmhcc RPMH_CXO_CLK>;
90        clock-names = "iface", "ref";
91    };
92