xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision ed7171ff9fabc49ae6ed42fbd082a576473836fc) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sa8775p-qmp-gen4x2-pcie-phy
20      - qcom,sa8775p-qmp-gen4x4-pcie-phy
21      - qcom,sc8180x-qmp-pcie-phy
22      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25      - qcom,sdm845-qhp-pcie-phy
26      - qcom,sdm845-qmp-pcie-phy
27      - qcom,sdx55-qmp-pcie-phy
28      - qcom,sdx65-qmp-gen4x2-pcie-phy
29      - qcom,sm8150-qmp-gen3x1-pcie-phy
30      - qcom,sm8150-qmp-gen3x2-pcie-phy
31      - qcom,sm8250-qmp-gen3x1-pcie-phy
32      - qcom,sm8250-qmp-gen3x2-pcie-phy
33      - qcom,sm8250-qmp-modem-pcie-phy
34      - qcom,sm8350-qmp-gen3x1-pcie-phy
35      - qcom,sm8450-qmp-gen3x1-pcie-phy
36      - qcom,sm8450-qmp-gen4x2-pcie-phy
37      - qcom,sm8550-qmp-gen3x2-pcie-phy
38      - qcom,sm8550-qmp-gen4x2-pcie-phy
39      - qcom,sm8650-qmp-gen3x2-pcie-phy
40      - qcom,sm8650-qmp-gen4x2-pcie-phy
41      - qcom,x1e80100-qmp-gen3x2-pcie-phy
42      - qcom,x1e80100-qmp-gen4x2-pcie-phy
43
44  reg:
45    minItems: 1
46    maxItems: 2
47
48  clocks:
49    minItems: 5
50    maxItems: 7
51
52  clock-names:
53    minItems: 5
54    items:
55      - const: aux
56      - const: cfg_ahb
57      - const: ref
58      - enum: [rchng, refgen]
59      - const: pipe
60      - const: pipediv2
61      - const: phy_aux
62
63  power-domains:
64    maxItems: 1
65
66  resets:
67    minItems: 1
68    maxItems: 2
69
70  reset-names:
71    minItems: 1
72    items:
73      - const: phy
74      - const: phy_nocsr
75
76  vdda-phy-supply: true
77
78  vdda-pll-supply: true
79
80  vdda-qref-supply: true
81
82  qcom,4ln-config-sel:
83    description: PCIe 4-lane configuration
84    $ref: /schemas/types.yaml#/definitions/phandle-array
85    items:
86      - items:
87          - description: phandle of TCSR syscon
88          - description: offset of PCIe 4-lane configuration register
89          - description: offset of configuration bit for this PHY
90
91  "#clock-cells": true
92
93  clock-output-names:
94    maxItems: 1
95
96  "#phy-cells":
97    const: 0
98
99required:
100  - compatible
101  - reg
102  - clocks
103  - clock-names
104  - resets
105  - reset-names
106  - vdda-phy-supply
107  - vdda-pll-supply
108  - "#clock-cells"
109  - clock-output-names
110  - "#phy-cells"
111
112additionalProperties: false
113
114allOf:
115  - if:
116      properties:
117        compatible:
118          contains:
119            enum:
120              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
121    then:
122      properties:
123        reg:
124          items:
125            - description: port a
126            - description: port b
127      required:
128        - qcom,4ln-config-sel
129    else:
130      properties:
131        reg:
132          maxItems: 1
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            enum:
139              - qcom,sc8180x-qmp-pcie-phy
140              - qcom,sdm845-qhp-pcie-phy
141              - qcom,sdm845-qmp-pcie-phy
142              - qcom,sdx55-qmp-pcie-phy
143              - qcom,sm8150-qmp-gen3x1-pcie-phy
144              - qcom,sm8150-qmp-gen3x2-pcie-phy
145              - qcom,sm8250-qmp-gen3x1-pcie-phy
146              - qcom,sm8250-qmp-gen3x2-pcie-phy
147              - qcom,sm8250-qmp-modem-pcie-phy
148              - qcom,sm8350-qmp-gen3x1-pcie-phy
149              - qcom,sm8450-qmp-gen3x1-pcie-phy
150              - qcom,sm8450-qmp-gen3x2-pcie-phy
151              - qcom,sm8550-qmp-gen3x2-pcie-phy
152              - qcom,sm8550-qmp-gen4x2-pcie-phy
153              - qcom,sm8650-qmp-gen3x2-pcie-phy
154              - qcom,sm8650-qmp-gen4x2-pcie-phy
155              - qcom,x1e80100-qmp-gen3x2-pcie-phy
156              - qcom,x1e80100-qmp-gen4x2-pcie-phy
157    then:
158      properties:
159        clocks:
160          maxItems: 5
161        clock-names:
162          maxItems: 5
163
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
170              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
171              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
172    then:
173      properties:
174        clocks:
175          minItems: 6
176        clock-names:
177          minItems: 6
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - qcom,sa8775p-qmp-gen4x2-pcie-phy
185              - qcom,sa8775p-qmp-gen4x4-pcie-phy
186    then:
187      properties:
188        clocks:
189          minItems: 7
190        clock-names:
191          minItems: 7
192
193  - if:
194      properties:
195        compatible:
196          contains:
197            enum:
198              - qcom,sm8550-qmp-gen4x2-pcie-phy
199              - qcom,sm8650-qmp-gen4x2-pcie-phy
200              - qcom,x1e80100-qmp-gen4x2-pcie-phy
201    then:
202      properties:
203        resets:
204          minItems: 2
205        reset-names:
206          minItems: 2
207    else:
208      properties:
209        resets:
210          maxItems: 1
211        reset-names:
212          maxItems: 1
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            enum:
219              - qcom,sm8450-qmp-gen4x2-pcie-phy
220              - qcom,sm8550-qmp-gen4x2-pcie-phy
221              - qcom,sm8650-qmp-gen4x2-pcie-phy
222    then:
223      properties:
224        "#clock-cells":
225          const: 1
226    else:
227      properties:
228        "#clock-cells":
229          const: 0
230
231examples:
232  - |
233    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
234
235    pcie2b_phy: phy@1c18000 {
236      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
237      reg = <0x01c18000 0x2000>;
238
239      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
240               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
241               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
242               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
243               <&gcc GCC_PCIE_2B_PIPE_CLK>,
244               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
245      clock-names = "aux", "cfg_ahb", "ref", "rchng",
246                    "pipe", "pipediv2";
247
248      power-domains = <&gcc PCIE_2B_GDSC>;
249
250      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
251      reset-names = "phy";
252
253      vdda-phy-supply = <&vreg_l6d>;
254      vdda-pll-supply = <&vreg_l4d>;
255
256      #clock-cells = <0>;
257      clock-output-names = "pcie_2b_pipe_clk";
258
259      #phy-cells = <0>;
260    };
261
262    pcie2a_phy: phy@1c24000 {
263      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
264      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
265
266      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
267               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
268               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
269               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
270               <&gcc GCC_PCIE_2A_PIPE_CLK>,
271               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
272      clock-names = "aux", "cfg_ahb", "ref", "rchng",
273                    "pipe", "pipediv2";
274
275      power-domains = <&gcc PCIE_2A_GDSC>;
276
277      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
278      reset-names = "phy";
279
280      vdda-phy-supply = <&vreg_l6d>;
281      vdda-pll-supply = <&vreg_l4d>;
282
283      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
284
285      #clock-cells = <0>;
286      clock-output-names = "pcie_2a_pipe_clk";
287
288      #phy-cells = <0>;
289    };
290