xref: /linux/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1*505fb254SDmitry Baryshkov# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*505fb254SDmitry Baryshkov%YAML 1.2
3*505fb254SDmitry Baryshkov---
4*505fb254SDmitry Baryshkov$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml#
5*505fb254SDmitry Baryshkov$schema: http://devicetree.org/meta-schemas/core.yaml#
6*505fb254SDmitry Baryshkov
7*505fb254SDmitry Baryshkovtitle: Qualcomm QMP PHY controller (PCIe, MSM8998)
8*505fb254SDmitry Baryshkov
9*505fb254SDmitry Baryshkovmaintainers:
10*505fb254SDmitry Baryshkov  - Vinod Koul <vkoul@kernel.org>
11*505fb254SDmitry Baryshkov
12*505fb254SDmitry Baryshkovdescription:
13*505fb254SDmitry Baryshkov  The QMP PHY controller supports physical layer functionality for a number of
14*505fb254SDmitry Baryshkov  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15*505fb254SDmitry Baryshkov
16*505fb254SDmitry Baryshkovproperties:
17*505fb254SDmitry Baryshkov  compatible:
18*505fb254SDmitry Baryshkov    const: qcom,msm8998-qmp-pcie-phy
19*505fb254SDmitry Baryshkov
20*505fb254SDmitry Baryshkov  reg:
21*505fb254SDmitry Baryshkov    items:
22*505fb254SDmitry Baryshkov      - description: serdes
23*505fb254SDmitry Baryshkov
24*505fb254SDmitry Baryshkov  clocks:
25*505fb254SDmitry Baryshkov    maxItems: 4
26*505fb254SDmitry Baryshkov
27*505fb254SDmitry Baryshkov  clock-names:
28*505fb254SDmitry Baryshkov    items:
29*505fb254SDmitry Baryshkov      - const: aux
30*505fb254SDmitry Baryshkov      - const: cfg_ahb
31*505fb254SDmitry Baryshkov      - const: ref
32*505fb254SDmitry Baryshkov      - const: pipe
33*505fb254SDmitry Baryshkov
34*505fb254SDmitry Baryshkov  resets:
35*505fb254SDmitry Baryshkov    maxItems: 2
36*505fb254SDmitry Baryshkov
37*505fb254SDmitry Baryshkov  reset-names:
38*505fb254SDmitry Baryshkov    items:
39*505fb254SDmitry Baryshkov      - const: phy
40*505fb254SDmitry Baryshkov      - const: common
41*505fb254SDmitry Baryshkov
42*505fb254SDmitry Baryshkov  vdda-phy-supply: true
43*505fb254SDmitry Baryshkov
44*505fb254SDmitry Baryshkov  vdda-pll-supply: true
45*505fb254SDmitry Baryshkov
46*505fb254SDmitry Baryshkov  "#clock-cells":
47*505fb254SDmitry Baryshkov    const: 0
48*505fb254SDmitry Baryshkov
49*505fb254SDmitry Baryshkov  clock-output-names:
50*505fb254SDmitry Baryshkov    maxItems: 1
51*505fb254SDmitry Baryshkov
52*505fb254SDmitry Baryshkov  "#phy-cells":
53*505fb254SDmitry Baryshkov    const: 0
54*505fb254SDmitry Baryshkov
55*505fb254SDmitry Baryshkovrequired:
56*505fb254SDmitry Baryshkov  - compatible
57*505fb254SDmitry Baryshkov  - reg
58*505fb254SDmitry Baryshkov  - clocks
59*505fb254SDmitry Baryshkov  - clock-names
60*505fb254SDmitry Baryshkov  - resets
61*505fb254SDmitry Baryshkov  - reset-names
62*505fb254SDmitry Baryshkov  - vdda-phy-supply
63*505fb254SDmitry Baryshkov  - vdda-pll-supply
64*505fb254SDmitry Baryshkov  - "#clock-cells"
65*505fb254SDmitry Baryshkov  - clock-output-names
66*505fb254SDmitry Baryshkov  - "#phy-cells"
67*505fb254SDmitry Baryshkov
68*505fb254SDmitry BaryshkovadditionalProperties: false
69*505fb254SDmitry Baryshkov
70*505fb254SDmitry Baryshkovexamples:
71*505fb254SDmitry Baryshkov  - |
72*505fb254SDmitry Baryshkov    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
73*505fb254SDmitry Baryshkov
74*505fb254SDmitry Baryshkov    phy@1c18000 {
75*505fb254SDmitry Baryshkov        compatible = "qcom,msm8998-qmp-pcie-phy";
76*505fb254SDmitry Baryshkov        reg = <0x01c06000 0x1000>;
77*505fb254SDmitry Baryshkov
78*505fb254SDmitry Baryshkov        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
79*505fb254SDmitry Baryshkov                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
80*505fb254SDmitry Baryshkov                 <&gcc GCC_PCIE_CLKREF_CLK>,
81*505fb254SDmitry Baryshkov                 <&gcc GCC_PCIE_0_PIPE_CLK>;
82*505fb254SDmitry Baryshkov        clock-names = "aux",
83*505fb254SDmitry Baryshkov                      "cfg_ahb",
84*505fb254SDmitry Baryshkov                      "ref",
85*505fb254SDmitry Baryshkov                      "pipe";
86*505fb254SDmitry Baryshkov
87*505fb254SDmitry Baryshkov        clock-output-names = "pcie_0_pipe_clk_src";
88*505fb254SDmitry Baryshkov        #clock-cells = <0>;
89*505fb254SDmitry Baryshkov
90*505fb254SDmitry Baryshkov        #phy-cells = <0>;
91*505fb254SDmitry Baryshkov
92*505fb254SDmitry Baryshkov        resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
93*505fb254SDmitry Baryshkov        reset-names = "phy", "common";
94*505fb254SDmitry Baryshkov
95*505fb254SDmitry Baryshkov        vdda-phy-supply = <&vreg_l1a_0p875>;
96*505fb254SDmitry Baryshkov        vdda-pll-supply = <&vreg_l2a_1p2>;
97*505fb254SDmitry Baryshkov    };
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