1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics STM32 USB HS PHY controller 8 9description: 10 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 14 PLL configuration. 15 16 USBPHYC 17 |_ PLL 18 | 19 |_ PHY port#1 _________________ HOST controller 20 | __ | 21 | / 1|________________| 22 |_ PHY port#2 ----| |________________ 23 | \_0| | 24 |_ UTMI switch_______| OTG controller 25 26maintainers: 27 - Amelie Delaunay <amelie.delaunay@foss.st.com> 28 29properties: 30 compatible: 31 const: st,stm32mp1-usbphyc 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 1 38 39 resets: 40 maxItems: 1 41 42 "#address-cells": 43 const: 1 44 45 "#size-cells": 46 const: 0 47 48 vdda1v1-supply: 49 description: regulator providing 1V1 power supply to the PLL block 50 51 vdda1v8-supply: 52 description: regulator providing 1V8 power supply to the PLL block 53 54 '#clock-cells': 55 description: number of clock cells for ck_usbo_48m consumer 56 const: 0 57 58 access-controllers: 59 minItems: 1 60 maxItems: 2 61 62# Required child nodes: 63 64patternProperties: 65 "^usb-phy@[0|1]$": 66 type: object 67 description: 68 Each port the controller provides must be represented as a sub-node. 69 70 properties: 71 reg: 72 description: phy port index. 73 maxItems: 1 74 75 phy-supply: 76 description: regulator providing 3V3 power supply to the PHY. 77 78 "#phy-cells": 79 enum: [ 0x0, 0x1 ] 80 81 connector: 82 type: object 83 $ref: /schemas/connector/usb-connector.yaml 84 unevaluatedProperties: false 85 86 properties: 87 vbus-supply: true 88 89 # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due 90 # to USB connector/receptacle, routing, ESD protection component,... Here is the list of 91 # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- 92 # Speed, LS for Low-Speed) 93 94 st,current-boost-microamp: 95 description: Current boosting in uA 96 enum: [ 1000, 2000 ] 97 98 st,no-lsfs-fb-cap: 99 description: Disables the LS/FS feedback capacitor 100 type: boolean 101 102 st,decrease-hs-slew-rate: 103 description: Decreases the HS driver slew rate by 10% 104 type: boolean 105 106 st,tune-hs-dc-level: 107 description: | 108 Tunes the HS driver DC level 109 - <0> normal level 110 - <1> increases the level by 5 to 7 mV 111 - <2> increases the level by 10 to 14 mV 112 - <3> decreases the level by 5 to 7 mV 113 $ref: /schemas/types.yaml#/definitions/uint32 114 minimum: 0 115 maximum: 3 116 default: 0 117 118 st,enable-fs-rftime-tuning: 119 description: Enables the FS rise/fall tuning option 120 type: boolean 121 122 st,enable-hs-rftime-reduction: 123 description: Enables the HS rise/fall reduction feature 124 type: boolean 125 126 st,trim-hs-current: 127 description: | 128 Controls HS driver current trimming for choke compensation 129 - <0> = 18.87 mA target current / nominal + 0% 130 - <1> = 19.165 mA target current / nominal + 1.56% 131 - <2> = 19.46 mA target current / nominal + 3.12% 132 - <3> = 19.755 mA target current / nominal + 4.68% 133 - <4> = 20.05 mA target current / nominal + 6.24% 134 - <5> = 20.345 mA target current / nominal + 7.8% 135 - <6> = 20.64 mA target current / nominal + 9.36% 136 - <7> = 20.935 mA target current / nominal + 10.92% 137 - <8> = 21.23 mA target current / nominal + 12.48% 138 - <9> = 21.525 mA target current / nominal + 14.04% 139 - <10> = 21.82 mA target current / nominal + 15.6% 140 - <11> = 22.115 mA target current / nominal + 17.16% 141 - <12> = 22.458 mA target current / nominal + 19.01% 142 - <13> = 22.755 mA target current / nominal + 20.58% 143 - <14> = 23.052 mA target current / nominal + 22.16% 144 - <15> = 23.348 mA target current / nominal + 23.73% 145 $ref: /schemas/types.yaml#/definitions/uint32 146 minimum: 0 147 maximum: 15 148 default: 0 149 150 st,trim-hs-impedance: 151 description: | 152 Controls HS driver impedance tuning for choke compensation 153 - <0> = no impedance offset 154 - <1> = reduce the impedance by 2 ohms 155 - <2> = reduce the impedance by 4 ohms 156 - <3> = reduce the impedance by 6 ohms 157 $ref: /schemas/types.yaml#/definitions/uint32 158 minimum: 0 159 maximum: 3 160 default: 0 161 162 st,tune-squelch-level: 163 description: | 164 Tunes the squelch DC threshold value 165 - <0> = no shift in threshold 166 - <1> = threshold shift by +7 mV 167 - <2> = threshold shift by -5 mV 168 - <3> = threshold shift by +14 mV 169 $ref: /schemas/types.yaml#/definitions/uint32 170 minimum: 0 171 maximum: 3 172 default: 0 173 174 st,enable-hs-rx-gain-eq: 175 description: Enables the HS Rx gain equalizer 176 type: boolean 177 178 st,tune-hs-rx-offset: 179 description: | 180 Adjusts the HS Rx offset 181 - <0> = no offset 182 - <1> = offset of +5 mV 183 - <2> = offset of +10 mV 184 - <3> = offset of -5 mV 185 $ref: /schemas/types.yaml#/definitions/uint32 186 minimum: 0 187 maximum: 3 188 default: 0 189 190 st,no-hs-ftime-ctrl: 191 description: Disables the HS fall time control of single ended signals during pre-emphasis 192 type: boolean 193 194 st,no-lsfs-sc: 195 description: Disables the short circuit protection in LS/FS driver 196 type: boolean 197 198 st,enable-hs-tx-staggering: 199 description: Enables the basic staggering in HS Tx mode 200 type: boolean 201 202 allOf: 203 - if: 204 properties: 205 reg: 206 const: 0 207 then: 208 properties: 209 "#phy-cells": 210 const: 0 211 else: 212 properties: 213 "#phy-cells": 214 const: 1 215 description: 216 The value is used to select UTMI switch output. 217 0 for OTG controller and 1 for Host controller. 218 219 required: 220 - reg 221 - phy-supply 222 - "#phy-cells" 223 224 additionalProperties: false 225 226required: 227 - compatible 228 - reg 229 - clocks 230 - "#address-cells" 231 - "#size-cells" 232 - vdda1v1-supply 233 - vdda1v8-supply 234 - usb-phy@0 235 - usb-phy@1 236 237additionalProperties: false 238 239examples: 240 - | 241 #include <dt-bindings/clock/stm32mp1-clks.h> 242 #include <dt-bindings/reset/stm32mp1-resets.h> 243 usbphyc: usbphyc@5a006000 { 244 compatible = "st,stm32mp1-usbphyc"; 245 reg = <0x5a006000 0x1000>; 246 clocks = <&rcc USBPHY_K>; 247 resets = <&rcc USBPHY_R>; 248 vdda1v1-supply = <®11>; 249 vdda1v8-supply = <®18>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 #clock-cells = <0>; 253 254 usbphyc_port0: usb-phy@0 { 255 reg = <0>; 256 phy-supply = <&vdd_usb>; 257 #phy-cells = <0>; 258 st,tune-hs-dc-level = <2>; 259 st,enable-fs-rftime-tuning; 260 st,enable-hs-rftime-reduction; 261 st,trim-hs-current = <15>; 262 st,trim-hs-impedance = <1>; 263 st,tune-squelch-level = <3>; 264 st,tune-hs-rx-offset = <2>; 265 st,no-lsfs-sc; 266 connector { 267 compatible = "usb-a-connector"; 268 vbus-supply = <&vbus_sw>; 269 }; 270 }; 271 272 usbphyc_port1: usb-phy@1 { 273 reg = <1>; 274 phy-supply = <&vdd_usb>; 275 #phy-cells = <1>; 276 st,tune-hs-dc-level = <2>; 277 st,enable-fs-rftime-tuning; 278 st,enable-hs-rftime-reduction; 279 st,trim-hs-current = <15>; 280 st,trim-hs-impedance = <1>; 281 st,tune-squelch-level = <3>; 282 st,tune-hs-rx-offset = <2>; 283 st,no-lsfs-sc; 284 }; 285 }; 286... 287