xref: /linux/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip USBDP Combo PHY with Samsung IP block
8
9maintainers:
10  - Frank Wang <frank.wang@rock-chips.com>
11  - Zhang Yubing <yubing.zhang@rock-chips.com>
12
13properties:
14  compatible:
15    enum:
16      - rockchip,rk3576-usbdp-phy
17      - rockchip,rk3588-usbdp-phy
18
19  reg:
20    maxItems: 1
21
22  "#phy-cells":
23    description: |
24      Cell allows setting the type of the PHY. Possible values are:
25      - PHY_TYPE_USB3
26      - PHY_TYPE_DP
27    const: 1
28
29  clocks:
30    maxItems: 4
31
32  clock-names:
33    items:
34      - const: refclk
35      - const: immortal
36      - const: pclk
37      - const: utmi
38
39  resets:
40    maxItems: 5
41
42  reset-names:
43    items:
44      - const: init
45      - const: cmn
46      - const: lane
47      - const: pcs_apb
48      - const: pma_apb
49
50  rockchip,dp-lane-mux:
51    $ref: /schemas/types.yaml#/definitions/uint32-array
52    minItems: 2
53    maxItems: 4
54    items:
55      maximum: 3
56    description:
57      An array of physical Type-C lanes indexes. Position of an entry
58      determines the DisplayPort (DP) lane index, while the value of an entry
59      indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
60      e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
61      3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
62      lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
63      <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
64      phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
65      DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
66
67  rockchip,u2phy-grf:
68    $ref: /schemas/types.yaml#/definitions/phandle
69    description:
70      Phandle to the syscon managing the 'usb2 phy general register files'.
71
72  rockchip,usb-grf:
73    $ref: /schemas/types.yaml#/definitions/phandle
74    description:
75      Phandle to the syscon managing the 'usb general register files'.
76
77  rockchip,usbdpphy-grf:
78    $ref: /schemas/types.yaml#/definitions/phandle
79    description:
80      Phandle to the syscon managing the 'usbdp phy general register files'.
81
82  rockchip,vo-grf:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description:
85      Phandle to the syscon managing the 'video output general register files'.
86      When select the DP lane mapping will request its phandle.
87
88  sbu1-dc-gpios:
89    description:
90      GPIO connected to the SBU1 line of the USB-C connector via a big resistor
91      (~100K) to apply a DC offset for signalling the connector orientation.
92    maxItems: 1
93
94  sbu2-dc-gpios:
95    description:
96      GPIO connected to the SBU2 line of the USB-C connector via a big resistor
97      (~100K) to apply a DC offset for signalling the connector orientation.
98    maxItems: 1
99
100  orientation-switch:
101    description: Flag the port as possible handler of orientation switching
102    type: boolean
103
104  mode-switch:
105    description: Flag the port as possible handler of altmode switching
106    type: boolean
107
108  port:
109    $ref: /schemas/graph.yaml#/properties/port
110    description:
111      A port node to link the PHY to a TypeC controller for the purpose of
112      handling orientation switching.
113
114required:
115  - compatible
116  - reg
117  - clocks
118  - clock-names
119  - resets
120  - reset-names
121  - "#phy-cells"
122
123additionalProperties: false
124
125examples:
126  - |
127    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
128    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
129
130    usbdp_phy0: phy@fed80000 {
131      compatible = "rockchip,rk3588-usbdp-phy";
132      reg = <0xfed80000 0x10000>;
133      #phy-cells = <1>;
134      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
135               <&cru CLK_USBDP_PHY0_IMMORTAL>,
136               <&cru PCLK_USBDPPHY0>,
137               <&u2phy0>;
138      clock-names = "refclk", "immortal", "pclk", "utmi";
139      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
140               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
141               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
142               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
143               <&cru SRST_P_USBDPPHY0>;
144      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
145      rockchip,u2phy-grf = <&usb2phy0_grf>;
146      rockchip,usb-grf = <&usb_grf>;
147      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
148      rockchip,vo-grf = <&vo0_grf>;
149    };
150