xref: /linux/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip USBDP Combo PHY with Samsung IP block
8
9maintainers:
10  - Frank Wang <frank.wang@rock-chips.com>
11  - Zhang Yubing <yubing.zhang@rock-chips.com>
12
13properties:
14  compatible:
15    enum:
16      - rockchip,rk3588-usbdp-phy
17
18  reg:
19    maxItems: 1
20
21  "#phy-cells":
22    description: |
23      Cell allows setting the type of the PHY. Possible values are:
24      - PHY_TYPE_USB3
25      - PHY_TYPE_DP
26    const: 1
27
28  clocks:
29    maxItems: 4
30
31  clock-names:
32    items:
33      - const: refclk
34      - const: immortal
35      - const: pclk
36      - const: utmi
37
38  resets:
39    maxItems: 5
40
41  reset-names:
42    items:
43      - const: init
44      - const: cmn
45      - const: lane
46      - const: pcs_apb
47      - const: pma_apb
48
49  rockchip,dp-lane-mux:
50    $ref: /schemas/types.yaml#/definitions/uint32-array
51    minItems: 2
52    maxItems: 4
53    items:
54      maximum: 3
55    description:
56      An array of physical Type-C lanes indexes. Position of an entry
57      determines the DisplayPort (DP) lane index, while the value of an entry
58      indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
59      e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
60      3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
61      lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
62      <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
63      phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
64      DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
65
66  rockchip,u2phy-grf:
67    $ref: /schemas/types.yaml#/definitions/phandle
68    description:
69      Phandle to the syscon managing the 'usb2 phy general register files'.
70
71  rockchip,usb-grf:
72    $ref: /schemas/types.yaml#/definitions/phandle
73    description:
74      Phandle to the syscon managing the 'usb general register files'.
75
76  rockchip,usbdpphy-grf:
77    $ref: /schemas/types.yaml#/definitions/phandle
78    description:
79      Phandle to the syscon managing the 'usbdp phy general register files'.
80
81  rockchip,vo-grf:
82    $ref: /schemas/types.yaml#/definitions/phandle
83    description:
84      Phandle to the syscon managing the 'video output general register files'.
85      When select the DP lane mapping will request its phandle.
86
87  sbu1-dc-gpios:
88    description:
89      GPIO connected to the SBU1 line of the USB-C connector via a big resistor
90      (~100K) to apply a DC offset for signalling the connector orientation.
91    maxItems: 1
92
93  sbu2-dc-gpios:
94    description:
95      GPIO connected to the SBU2 line of the USB-C connector via a big resistor
96      (~100K) to apply a DC offset for signalling the connector orientation.
97    maxItems: 1
98
99  orientation-switch:
100    description: Flag the port as possible handler of orientation switching
101    type: boolean
102
103  mode-switch:
104    description: Flag the port as possible handler of altmode switching
105    type: boolean
106
107  port:
108    $ref: /schemas/graph.yaml#/properties/port
109    description:
110      A port node to link the PHY to a TypeC controller for the purpose of
111      handling orientation switching.
112
113required:
114  - compatible
115  - reg
116  - clocks
117  - clock-names
118  - resets
119  - reset-names
120  - "#phy-cells"
121
122additionalProperties: false
123
124examples:
125  - |
126    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
127    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
128
129    usbdp_phy0: phy@fed80000 {
130      compatible = "rockchip,rk3588-usbdp-phy";
131      reg = <0xfed80000 0x10000>;
132      #phy-cells = <1>;
133      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
134               <&cru CLK_USBDP_PHY0_IMMORTAL>,
135               <&cru PCLK_USBDPPHY0>,
136               <&u2phy0>;
137      clock-names = "refclk", "immortal", "pclk", "utmi";
138      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
139               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
140               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
141               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
142               <&cru SRST_P_USBDPPHY0>;
143      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
144      rockchip,u2phy-grf = <&usb2phy0_grf>;
145      rockchip,usb-grf = <&usb_grf>;
146      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
147      rockchip,vo-grf = <&vo0_grf>;
148    };
149