xref: /linux/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml (revision df9c299371054cb725eef730fd0f1d0fe2ed6bb0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3562-naneng-combphy
16      - rockchip,rk3568-naneng-combphy
17      - rockchip,rk3576-naneng-combphy
18      - rockchip,rk3588-naneng-combphy
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    items:
25      - description: reference clock
26      - description: apb clock
27      - description: pipe clock
28
29  clock-names:
30    items:
31      - const: ref
32      - const: apb
33      - const: pipe
34
35  resets:
36    minItems: 1
37    maxItems: 2
38
39  reset-names:
40    minItems: 1
41    items:
42      - const: phy
43      - const: apb
44
45  phy-supply:
46    description: Single PHY regulator
47
48  rockchip,enable-ssc:
49    type: boolean
50    description:
51      The option SSC can be enabled for U3, SATA and PCIE.
52      Most commercially available platforms use SSC to reduce EMI.
53
54  rockchip,ext-refclk:
55    type: boolean
56    description:
57      Many PCIe connections, especially backplane connections,
58      require a synchronous reference clock between the two link partners.
59      To achieve this a common clock source, referred to as REFCLK in
60      the PCI Express Card Electromechanical Specification,
61      should be used by both ends of the PCIe link.
62      In PCIe mode one can choose to use an internal or an external reference
63      clock.
64      By default the internal clock is selected. The PCIe PHY provides a 100MHz
65      differential clock output(optional with SSC) for system applications.
66      When selecting this option an externally 100MHz differential
67      reference clock needs to be provided to the PCIe PHY.
68
69  rockchip,pipe-grf:
70    $ref: /schemas/types.yaml#/definitions/phandle
71    description:
72      Some additional phy settings are accessed through GRF regs.
73
74  rockchip,pipe-phy-grf:
75    $ref: /schemas/types.yaml#/definitions/phandle
76    description:
77      Some additional pipe settings are accessed through GRF regs.
78
79  "#phy-cells":
80    const: 1
81
82required:
83  - compatible
84  - reg
85  - clocks
86  - clock-names
87  - resets
88  - rockchip,pipe-grf
89  - rockchip,pipe-phy-grf
90  - "#phy-cells"
91
92allOf:
93  - if:
94      properties:
95        compatible:
96          contains:
97            const: rockchip,rk3568-naneng-combphy
98    then:
99      properties:
100        resets:
101          maxItems: 1
102        reset-names:
103          maxItems: 1
104  - if:
105      properties:
106        compatible:
107          contains:
108            const: rockchip,rk3588-naneng-combphy
109    then:
110      properties:
111        resets:
112          minItems: 2
113        reset-names:
114          minItems: 2
115      required:
116        - reset-names
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/clock/rk3568-cru.h>
123
124    pipegrf: syscon@fdc50000 {
125      compatible = "rockchip,rk3568-pipe-grf", "syscon";
126      reg = <0xfdc50000 0x1000>;
127    };
128
129    pipe_phy_grf0: syscon@fdc70000 {
130      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
131      reg = <0xfdc70000 0x1000>;
132    };
133
134    combphy0: phy@fe820000 {
135      compatible = "rockchip,rk3568-naneng-combphy";
136      reg = <0xfe820000 0x100>;
137      clocks = <&pmucru CLK_PCIEPHY0_REF>,
138               <&cru PCLK_PIPEPHY0>,
139               <&cru PCLK_PIPE>;
140      clock-names = "ref", "apb", "pipe";
141      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
142      assigned-clock-rates = <100000000>;
143      resets = <&cru SRST_PIPEPHY0>;
144      rockchip,pipe-grf = <&pipegrf>;
145      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
146      #phy-cells = <1>;
147    };
148