xref: /linux/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml (revision dec1c62e91ba268ab2a6e339d4d7a59287d5eba1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3568-naneng-combphy
16
17  reg:
18    maxItems: 1
19
20  clocks:
21    items:
22      - description: reference clock
23      - description: apb clock
24      - description: pipe clock
25
26  clock-names:
27    items:
28      - const: ref
29      - const: apb
30      - const: pipe
31
32  resets:
33    items:
34      - description: exclusive PHY reset line
35
36  rockchip,enable-ssc:
37    type: boolean
38    description:
39      The option SSC can be enabled for U3, SATA and PCIE.
40      Most commercially available platforms use SSC to reduce EMI.
41
42  rockchip,ext-refclk:
43    type: boolean
44    description:
45      Many PCIe connections, especially backplane connections,
46      require a synchronous reference clock between the two link partners.
47      To achieve this a common clock source, referred to as REFCLK in
48      the PCI Express Card Electromechanical Specification,
49      should be used by both ends of the PCIe link.
50      In PCIe mode one can choose to use an internal or an external reference
51      clock.
52      By default the internal clock is selected. The PCIe PHY provides a 100MHz
53      differential clock output(optional with SSC) for system applications.
54      When selecting this option an externally 100MHz differential
55      reference clock needs to be provided to the PCIe PHY.
56
57  rockchip,pipe-grf:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      Some additional phy settings are accessed through GRF regs.
61
62  rockchip,pipe-phy-grf:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    description:
65      Some additional pipe settings are accessed through GRF regs.
66
67  "#phy-cells":
68    const: 1
69
70required:
71  - compatible
72  - reg
73  - clocks
74  - clock-names
75  - resets
76  - rockchip,pipe-grf
77  - rockchip,pipe-phy-grf
78  - "#phy-cells"
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/rk3568-cru.h>
85
86    pipegrf: syscon@fdc50000 {
87      compatible = "rockchip,rk3568-pipe-grf", "syscon";
88      reg = <0xfdc50000 0x1000>;
89    };
90
91    pipe_phy_grf0: syscon@fdc70000 {
92      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
93      reg = <0xfdc70000 0x1000>;
94    };
95
96    combphy0: phy@fe820000 {
97      compatible = "rockchip,rk3568-naneng-combphy";
98      reg = <0xfe820000 0x100>;
99      clocks = <&pmucru CLK_PCIEPHY0_REF>,
100               <&cru PCLK_PIPEPHY0>,
101               <&cru PCLK_PIPE>;
102      clock-names = "ref", "apb", "pipe";
103      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
104      assigned-clock-rates = <100000000>;
105      resets = <&cru SRST_PIPEPHY0>;
106      rockchip,pipe-grf = <&pipegrf>;
107      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
108      #phy-cells = <1>;
109    };
110