xref: /linux/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml (revision d8d2b1f81530988abe2e2bfaceec1c5d30b9a0b4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3528-naneng-combphy
16      - rockchip,rk3562-naneng-combphy
17      - rockchip,rk3568-naneng-combphy
18      - rockchip,rk3576-naneng-combphy
19      - rockchip,rk3588-naneng-combphy
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    items:
26      - description: reference clock
27      - description: apb clock
28      - description: pipe clock
29
30  clock-names:
31    items:
32      - const: ref
33      - const: apb
34      - const: pipe
35
36  resets:
37    minItems: 1
38    maxItems: 2
39
40  reset-names:
41    minItems: 1
42    items:
43      - const: phy
44      - const: apb
45
46  phy-supply:
47    description: Single PHY regulator
48
49  power-domains:
50    maxItems: 1
51
52  rockchip,enable-ssc:
53    type: boolean
54    description:
55      The option SSC can be enabled for U3, SATA and PCIE.
56      Most commercially available platforms use SSC to reduce EMI.
57
58  rockchip,ext-refclk:
59    type: boolean
60    description:
61      Many PCIe connections, especially backplane connections,
62      require a synchronous reference clock between the two link partners.
63      To achieve this a common clock source, referred to as REFCLK in
64      the PCI Express Card Electromechanical Specification,
65      should be used by both ends of the PCIe link.
66      In PCIe mode one can choose to use an internal or an external reference
67      clock.
68      By default the internal clock is selected. The PCIe PHY provides a 100MHz
69      differential clock output(optional with SSC) for system applications.
70      When selecting this option an externally 100MHz differential
71      reference clock needs to be provided to the PCIe PHY.
72
73  rockchip,pipe-grf:
74    $ref: /schemas/types.yaml#/definitions/phandle
75    description:
76      Some additional phy settings are accessed through GRF regs.
77
78  rockchip,pipe-phy-grf:
79    $ref: /schemas/types.yaml#/definitions/phandle
80    description:
81      Some additional pipe settings are accessed through GRF regs.
82
83  "#phy-cells":
84    const: 1
85
86required:
87  - compatible
88  - reg
89  - clocks
90  - clock-names
91  - resets
92  - rockchip,pipe-grf
93  - rockchip,pipe-phy-grf
94  - "#phy-cells"
95
96allOf:
97  - if:
98      properties:
99        compatible:
100          contains:
101            const: rockchip,rk3568-naneng-combphy
102    then:
103      properties:
104        resets:
105          maxItems: 1
106        reset-names:
107          maxItems: 1
108  - if:
109      properties:
110        compatible:
111          contains:
112            enum:
113              - rockchip,rk3528-naneng-combphy
114              - rockchip,rk3588-naneng-combphy
115    then:
116      properties:
117        resets:
118          minItems: 2
119        reset-names:
120          minItems: 2
121      required:
122        - reset-names
123
124additionalProperties: false
125
126examples:
127  - |
128    #include <dt-bindings/clock/rk3568-cru.h>
129
130    pipegrf: syscon@fdc50000 {
131      compatible = "rockchip,rk3568-pipe-grf", "syscon";
132      reg = <0xfdc50000 0x1000>;
133    };
134
135    pipe_phy_grf0: syscon@fdc70000 {
136      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
137      reg = <0xfdc70000 0x1000>;
138    };
139
140    combphy0: phy@fe820000 {
141      compatible = "rockchip,rk3568-naneng-combphy";
142      reg = <0xfe820000 0x100>;
143      clocks = <&pmucru CLK_PCIEPHY0_REF>,
144               <&cru PCLK_PIPEPHY0>,
145               <&cru PCLK_PIPE>;
146      clock-names = "ref", "apb", "pipe";
147      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
148      assigned-clock-rates = <100000000>;
149      resets = <&cru SRST_PIPEPHY0>;
150      rockchip,pipe-grf = <&pipegrf>;
151      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
152      #phy-cells = <1>;
153    };
154