1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence Torrent SD0801 PHY 8 9description: 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) 11 hardware included with the Cadence MHDP DisplayPort controller. Torrent 12 PHY also supports multilink multiprotocol combinations including protocols 13 such as PCIe, USB, SGMII, QSGMII etc. 14 15maintainers: 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 18 19properties: 20 compatible: 21 enum: 22 - cdns,torrent-phy 23 - ti,j7200-serdes-10g 24 - ti,j721e-serdes-10g 25 26 '#address-cells': 27 const: 1 28 29 '#size-cells': 30 const: 0 31 32 '#clock-cells': 33 const: 1 34 35 clocks: 36 minItems: 1 37 maxItems: 2 38 description: 39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1). 40 pll1_refclk is optional and used for multi-protocol configurations requiring 41 separate reference clock for each protocol. 42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used. 43 Optional parent clock (phy_en_refclk) to enable a reference clock output feature 44 on some platforms to output either derived or received reference clock. 45 46 clock-names: 47 minItems: 1 48 items: 49 - const: refclk 50 - enum: [ pll1_refclk, phy_en_refclk ] 51 52 reg: 53 minItems: 1 54 items: 55 - description: Offset of the Torrent PHY configuration registers. 56 - description: Offset of the DPTX PHY configuration registers. 57 58 reg-names: 59 minItems: 1 60 items: 61 - const: torrent_phy 62 - const: dptx_phy 63 64 resets: 65 minItems: 1 66 items: 67 - description: Torrent PHY reset. 68 - description: Torrent APB reset. This is optional. 69 70 reset-names: 71 minItems: 1 72 items: 73 - const: torrent_reset 74 - const: torrent_apb 75 76patternProperties: 77 '^phy@[0-3]$': 78 type: object 79 description: 80 Each group of PHY lanes with a single master lane should be represented as a sub-node. 81 properties: 82 reg: 83 description: 84 The master lane number. This is the lowest numbered lane in the lane group. 85 minimum: 0 86 maximum: 3 87 88 resets: 89 minItems: 1 90 maxItems: 4 91 description: 92 Contains list of resets, one per lane, to get all the link lanes out of reset. 93 94 "#phy-cells": 95 const: 0 96 97 cdns,phy-type: 98 description: 99 Specifies the type of PHY for which the group of PHY lanes is used. 100 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. 101 $ref: /schemas/types.yaml#/definitions/uint32 102 enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 12] 103 104 cdns,num-lanes: 105 description: 106 Number of lanes. 107 $ref: /schemas/types.yaml#/definitions/uint32 108 enum: [1, 2, 3, 4] 109 default: 4 110 111 cdns,ssc-mode: 112 description: 113 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, 114 EXTERNAL_SSC or INTERNAL_SSC. 115 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. 116 $ref: /schemas/types.yaml#/definitions/uint32 117 enum: [0, 1, 2] 118 default: 0 119 120 cdns,max-bit-rate: 121 description: 122 Maximum DisplayPort link bit rate to use, in Mbps 123 $ref: /schemas/types.yaml#/definitions/uint32 124 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] 125 default: 8100 126 127 required: 128 - reg 129 - resets 130 - "#phy-cells" 131 - cdns,phy-type 132 - cdns,num-lanes 133 134 additionalProperties: false 135 136required: 137 - compatible 138 - "#address-cells" 139 - "#size-cells" 140 - clocks 141 - clock-names 142 - reg 143 - reg-names 144 - resets 145 - reset-names 146 147additionalProperties: false 148 149examples: 150 - | 151 #include <dt-bindings/phy/phy.h> 152 153 bus { 154 #address-cells = <2>; 155 #size-cells = <2>; 156 157 torrent-phy@f0fb500000 { 158 compatible = "cdns,torrent-phy"; 159 reg = <0xf0 0xfb500000 0x0 0x00100000>, 160 <0xf0 0xfb030a00 0x0 0x00000040>; 161 reg-names = "torrent_phy", "dptx_phy"; 162 resets = <&phyrst 0>; 163 reset-names = "torrent_reset"; 164 clocks = <&ref_clk>; 165 clock-names = "refclk"; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 phy@0 { 169 reg = <0>; 170 resets = <&phyrst 1>, <&phyrst 2>, 171 <&phyrst 3>, <&phyrst 4>; 172 #phy-cells = <0>; 173 cdns,phy-type = <PHY_TYPE_DP>; 174 cdns,num-lanes = <4>; 175 cdns,max-bit-rate = <8100>; 176 }; 177 }; 178 }; 179 - | 180 #include <dt-bindings/phy/phy.h> 181 #include <dt-bindings/phy/phy-cadence.h> 182 183 bus { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 187 torrent-phy@f0fb500000 { 188 compatible = "cdns,torrent-phy"; 189 reg = <0xf0 0xfb500000 0x0 0x00100000>; 190 reg-names = "torrent_phy"; 191 resets = <&phyrst 0>, <&phyrst 1>; 192 reset-names = "torrent_reset", "torrent_apb"; 193 clocks = <&ref_clk>; 194 clock-names = "refclk"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 phy@0 { 198 reg = <0>; 199 resets = <&phyrst 2>, <&phyrst 3>; 200 #phy-cells = <0>; 201 cdns,phy-type = <PHY_TYPE_PCIE>; 202 cdns,num-lanes = <2>; 203 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 204 }; 205 206 phy@2 { 207 reg = <2>; 208 resets = <&phyrst 4>; 209 #phy-cells = <0>; 210 cdns,phy-type = <PHY_TYPE_SGMII>; 211 cdns,num-lanes = <1>; 212 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>; 213 }; 214 }; 215 }; 216... 217