xref: /linux/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml (revision fba5618451d2b3af5e55f8af5ce9c5d3677ad9c4)
15ffc259dSYuti Amonkar# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
25ffc259dSYuti Amonkar%YAML 1.2
35ffc259dSYuti Amonkar---
45ffc259dSYuti Amonkar$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
55ffc259dSYuti Amonkar$schema: "http://devicetree.org/meta-schemas/core.yaml#"
65ffc259dSYuti Amonkar
75ffc259dSYuti Amonkartitle: Cadence Torrent SD0801 PHY binding for DisplayPort
85ffc259dSYuti Amonkar
95ffc259dSYuti Amonkardescription:
105ffc259dSYuti Amonkar  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
115ffc259dSYuti Amonkar  hardware included with the Cadence MHDP DisplayPort controller.
125ffc259dSYuti Amonkar
135ffc259dSYuti Amonkarmaintainers:
145ffc259dSYuti Amonkar  - Swapnil Jakhade <sjakhade@cadence.com>
155ffc259dSYuti Amonkar  - Yuti Amonkar <yamonkar@cadence.com>
165ffc259dSYuti Amonkar
175ffc259dSYuti Amonkarproperties:
185ffc259dSYuti Amonkar  compatible:
195ffc259dSYuti Amonkar    enum:
205ffc259dSYuti Amonkar      - cdns,torrent-phy
215ffc259dSYuti Amonkar      - ti,j721e-serdes-10g
225ffc259dSYuti Amonkar
235ffc259dSYuti Amonkar  '#address-cells':
245ffc259dSYuti Amonkar    const: 1
255ffc259dSYuti Amonkar
265ffc259dSYuti Amonkar  '#size-cells':
275ffc259dSYuti Amonkar    const: 0
285ffc259dSYuti Amonkar
295ffc259dSYuti Amonkar  clocks:
305ffc259dSYuti Amonkar    maxItems: 1
315ffc259dSYuti Amonkar    description:
325ffc259dSYuti Amonkar      PHY reference clock. Must contain an entry in clock-names.
335ffc259dSYuti Amonkar
345ffc259dSYuti Amonkar  clock-names:
355ffc259dSYuti Amonkar    const: refclk
365ffc259dSYuti Amonkar
375ffc259dSYuti Amonkar  reg:
385ffc259dSYuti Amonkar    minItems: 1
395ffc259dSYuti Amonkar    maxItems: 2
405ffc259dSYuti Amonkar    items:
415ffc259dSYuti Amonkar      - description: Offset of the Torrent PHY configuration registers.
425ffc259dSYuti Amonkar      - description: Offset of the DPTX PHY configuration registers.
435ffc259dSYuti Amonkar
445ffc259dSYuti Amonkar  reg-names:
455ffc259dSYuti Amonkar    minItems: 1
465ffc259dSYuti Amonkar    maxItems: 2
475ffc259dSYuti Amonkar    items:
485ffc259dSYuti Amonkar      - const: torrent_phy
495ffc259dSYuti Amonkar      - const: dptx_phy
505ffc259dSYuti Amonkar
515ffc259dSYuti Amonkar  resets:
525ffc259dSYuti Amonkar    maxItems: 1
535ffc259dSYuti Amonkar    description:
545ffc259dSYuti Amonkar      Torrent PHY reset.
555ffc259dSYuti Amonkar      See Documentation/devicetree/bindings/reset/reset.txt
565ffc259dSYuti Amonkar
575ffc259dSYuti AmonkarpatternProperties:
585ffc259dSYuti Amonkar  '^phy@[0-7]+$':
595ffc259dSYuti Amonkar    type: object
605ffc259dSYuti Amonkar    description:
615ffc259dSYuti Amonkar      Each group of PHY lanes with a single master lane should be represented as a sub-node.
625ffc259dSYuti Amonkar    properties:
635ffc259dSYuti Amonkar      reg:
645ffc259dSYuti Amonkar        description:
655ffc259dSYuti Amonkar          The master lane number. This is the lowest numbered lane in the lane group.
665ffc259dSYuti Amonkar
675ffc259dSYuti Amonkar      resets:
685ffc259dSYuti Amonkar        minItems: 1
695ffc259dSYuti Amonkar        maxItems: 4
705ffc259dSYuti Amonkar        description:
715ffc259dSYuti Amonkar          Contains list of resets, one per lane, to get all the link lanes out of reset.
725ffc259dSYuti Amonkar
735ffc259dSYuti Amonkar      "#phy-cells":
745ffc259dSYuti Amonkar        const: 0
755ffc259dSYuti Amonkar
765ffc259dSYuti Amonkar      cdns,phy-type:
775ffc259dSYuti Amonkar        description:
785ffc259dSYuti Amonkar          Specifies the type of PHY for which the group of PHY lanes is used.
795ffc259dSYuti Amonkar          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
803d21a460SRob Herring        $ref: /schemas/types.yaml#/definitions/uint32
813d21a460SRob Herring        enum: [1, 2, 3, 4, 5, 6]
825ffc259dSYuti Amonkar
835ffc259dSYuti Amonkar      cdns,num-lanes:
845ffc259dSYuti Amonkar        description:
855ffc259dSYuti Amonkar          Number of DisplayPort lanes.
863d21a460SRob Herring        $ref: /schemas/types.yaml#/definitions/uint32
873d21a460SRob Herring        enum: [1, 2, 4]
885ffc259dSYuti Amonkar        default: 4
895ffc259dSYuti Amonkar
905ffc259dSYuti Amonkar      cdns,max-bit-rate:
915ffc259dSYuti Amonkar        description:
925ffc259dSYuti Amonkar          Maximum DisplayPort link bit rate to use, in Mbps
933d21a460SRob Herring        $ref: /schemas/types.yaml#/definitions/uint32
943d21a460SRob Herring        enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
955ffc259dSYuti Amonkar        default: 8100
965ffc259dSYuti Amonkar
975ffc259dSYuti Amonkar    required:
985ffc259dSYuti Amonkar      - reg
995ffc259dSYuti Amonkar      - resets
1005ffc259dSYuti Amonkar      - "#phy-cells"
1015ffc259dSYuti Amonkar      - cdns,phy-type
1025ffc259dSYuti Amonkar
1035ffc259dSYuti Amonkar    additionalProperties: false
1045ffc259dSYuti Amonkar
1055ffc259dSYuti Amonkarrequired:
1065ffc259dSYuti Amonkar  - compatible
1075ffc259dSYuti Amonkar  - "#address-cells"
1085ffc259dSYuti Amonkar  - "#size-cells"
1095ffc259dSYuti Amonkar  - clocks
1105ffc259dSYuti Amonkar  - clock-names
1115ffc259dSYuti Amonkar  - reg
1125ffc259dSYuti Amonkar  - reg-names
1135ffc259dSYuti Amonkar  - resets
1145ffc259dSYuti Amonkar
1155ffc259dSYuti AmonkaradditionalProperties: false
1165ffc259dSYuti Amonkar
1175ffc259dSYuti Amonkarexamples:
1185ffc259dSYuti Amonkar  - |
1195ffc259dSYuti Amonkar    #include <dt-bindings/phy/phy.h>
120*fba56184SRob Herring
121*fba56184SRob Herring    bus {
122*fba56184SRob Herring        #address-cells = <2>;
123*fba56184SRob Herring        #size-cells = <2>;
124*fba56184SRob Herring
125*fba56184SRob Herring        torrent-phy@f0fb500000 {
1265ffc259dSYuti Amonkar            compatible = "cdns,torrent-phy";
1275ffc259dSYuti Amonkar            reg = <0xf0 0xfb500000 0x0 0x00100000>,
1285ffc259dSYuti Amonkar                  <0xf0 0xfb030a00 0x0 0x00000040>;
1295ffc259dSYuti Amonkar            reg-names = "torrent_phy", "dptx_phy";
1305ffc259dSYuti Amonkar            resets = <&phyrst 0>;
1315ffc259dSYuti Amonkar            clocks = <&ref_clk>;
1325ffc259dSYuti Amonkar            clock-names = "refclk";
1335ffc259dSYuti Amonkar            #address-cells = <1>;
1345ffc259dSYuti Amonkar            #size-cells = <0>;
135*fba56184SRob Herring            phy@0 {
1365ffc259dSYuti Amonkar                      reg = <0>;
1375ffc259dSYuti Amonkar                      resets = <&phyrst 1>, <&phyrst 2>,
1385ffc259dSYuti Amonkar                               <&phyrst 3>, <&phyrst 4>;
1395ffc259dSYuti Amonkar                      #phy-cells = <0>;
1405ffc259dSYuti Amonkar                      cdns,phy-type = <PHY_TYPE_DP>;
1415ffc259dSYuti Amonkar                      cdns,num-lanes = <4>;
1425ffc259dSYuti Amonkar                      cdns,max-bit-rate = <8100>;
1435ffc259dSYuti Amonkar            };
1445ffc259dSYuti Amonkar        };
145*fba56184SRob Herring    };
1465ffc259dSYuti Amonkar...
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