xref: /linux/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra USB PHY
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14properties:
15  compatible:
16    oneOf:
17      - items:
18          - enum:
19              - nvidia,tegra124-usb-phy
20              - nvidia,tegra114-usb-phy
21          - enum:
22              - nvidia,tegra30-usb-phy
23      - items:
24          - enum:
25              - nvidia,tegra30-usb-phy
26              - nvidia,tegra20-usb-phy
27
28  reg:
29    minItems: 1
30    maxItems: 2
31    description: |
32      PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33      PHY0 and PHY2 must specify two register sets, where the first set is
34      PHY own registers and the second set is the PHY0 registers.
35
36  clocks:
37    anyOf:
38      - items:
39          - description: Registers clock
40          - description: Main PHY clock
41
42      - items:
43          - description: Registers clock
44          - description: Main PHY clock
45          - description: ULPI PHY clock
46
47      - items:
48          - description: Registers clock
49          - description: Main PHY clock
50          - description: UTMI pads control registers clock
51
52      - items:
53          - description: Registers clock
54          - description: Main PHY clock
55          - description: UTMI timeout clock
56          - description: UTMI pads control registers clock
57
58  clock-names:
59    oneOf:
60      - items:
61          - const: reg
62          - const: pll_u
63
64      - items:
65          - const: reg
66          - const: pll_u
67          - const: ulpi-link
68
69      - items:
70          - const: reg
71          - const: pll_u
72          - const: utmi-pads
73
74      - items:
75          - const: reg
76          - const: pll_u
77          - const: timer
78          - const: utmi-pads
79
80  interrupts:
81    maxItems: 1
82
83  resets:
84    oneOf:
85      - maxItems: 1
86        description: PHY reset
87
88      - items:
89          - description: PHY reset
90          - description: UTMI pads reset
91
92  reset-names:
93    oneOf:
94      - const: usb
95
96      - items:
97          - const: usb
98          - const: utmi-pads
99
100  "#phy-cells":
101    const: 0
102
103  phy_type:
104    $ref: /schemas/types.yaml#/definitions/string
105    enum: [utmi, ulpi, hsic]
106
107  dr_mode:
108    $ref: /schemas/types.yaml#/definitions/string
109    enum: [host, peripheral, otg]
110    default: host
111
112  vbus-supply:
113    description: Regulator controlling USB VBUS.
114
115  nvidia,has-legacy-mode:
116    description: |
117      Indicates whether this controller can operate in legacy mode
118      (as APX 2500 / 2600). In legacy mode some registers are accessed
119      through the APB_MISC base address instead of the USB controller.
120    type: boolean
121
122  nvidia,is-wired:
123    description: |
124      Indicates whether we can do certain kind of power optimizations for
125      the devices that are always connected. e.g. modem.
126    type: boolean
127
128  nvidia,has-utmi-pad-registers:
129    description: |
130      Indicates whether this controller contains the UTMI pad control
131      registers common to all USB controllers.
132    type: boolean
133
134  nvidia,hssync-start-delay:
135    $ref: /schemas/types.yaml#/definitions/uint32
136    minimum: 0
137    maximum: 31
138    description: |
139      Number of 480 MHz clock cycles to wait before start of sync launches
140      RxActive.
141
142  nvidia,elastic-limit:
143    $ref: /schemas/types.yaml#/definitions/uint32
144    minimum: 0
145    maximum: 31
146    description: Variable FIFO Depth of elastic input store.
147
148  nvidia,idle-wait-delay:
149    $ref: /schemas/types.yaml#/definitions/uint32
150    minimum: 0
151    maximum: 31
152    description: |
153      Number of 480 MHz clock cycles of idle to wait before declare IDLE.
154
155  nvidia,term-range-adj:
156    $ref: /schemas/types.yaml#/definitions/uint32
157    minimum: 0
158    maximum: 15
159    description: Range adjustment on terminations.
160
161  nvidia,xcvr-setup:
162    $ref: /schemas/types.yaml#/definitions/uint32
163    minimum: 0
164    maximum: 127
165    description: Input of XCVR cell, HS driver output control.
166
167  nvidia,xcvr-setup-use-fuses:
168    description: Indicates that the value is read from the on-chip fuses.
169    type: boolean
170
171  nvidia,xcvr-lsfslew:
172    $ref: /schemas/types.yaml#/definitions/uint32
173    minimum: 0
174    maximum: 3
175    description: LS falling slew rate control.
176
177  nvidia,xcvr-lsrslew:
178    $ref: /schemas/types.yaml#/definitions/uint32
179    minimum: 0
180    maximum: 3
181    description: LS rising slew rate control.
182
183  nvidia,xcvr-hsslew:
184    $ref: /schemas/types.yaml#/definitions/uint32
185    minimum: 0
186    maximum: 511
187    description: HS slew rate control.
188
189  nvidia,hssquelch-level:
190    $ref: /schemas/types.yaml#/definitions/uint32
191    minimum: 0
192    maximum: 3
193    description: HS squelch detector level.
194
195  nvidia,hsdiscon-level:
196    $ref: /schemas/types.yaml#/definitions/uint32
197    minimum: 0
198    maximum: 7
199    description: HS disconnect detector level.
200
201  nvidia,phy-reset-gpio:
202    maxItems: 1
203    description: GPIO used to reset the PHY.
204
205  nvidia,pmc:
206    $ref: /schemas/types.yaml#/definitions/phandle-array
207    items:
208      - items:
209          - description: Phandle to Power Management controller.
210          - description: USB controller ID.
211    description:
212      Phandle to Power Management controller.
213
214required:
215  - compatible
216  - reg
217  - clocks
218  - clock-names
219  - resets
220  - reset-names
221  - "#phy-cells"
222  - phy_type
223
224additionalProperties: false
225
226allOf:
227  - if:
228      properties:
229        phy_type:
230          const: utmi
231
232    then:
233      properties:
234        reg:
235          minItems: 2
236          maxItems: 2
237
238        resets:
239          maxItems: 2
240
241        reset-names:
242          maxItems: 2
243
244      required:
245        - nvidia,hssync-start-delay
246        - nvidia,elastic-limit
247        - nvidia,idle-wait-delay
248        - nvidia,term-range-adj
249        - nvidia,xcvr-lsfslew
250        - nvidia,xcvr-lsrslew
251
252      anyOf:
253        - required: ["nvidia,xcvr-setup"]
254        - required: ["nvidia,xcvr-setup-use-fuses"]
255
256      if:
257        properties:
258          compatible:
259            contains:
260              const: nvidia,tegra30-usb-phy
261
262      then:
263        properties:
264          clocks:
265            maxItems: 3
266
267          clock-names:
268            items:
269              - const: reg
270              - const: pll_u
271              - const: utmi-pads
272
273        required:
274          - nvidia,xcvr-hsslew
275          - nvidia,hssquelch-level
276          - nvidia,hsdiscon-level
277
278      else:
279        properties:
280          clocks:
281            maxItems: 4
282
283          clock-names:
284            items:
285              - const: reg
286              - const: pll_u
287              - const: timer
288              - const: utmi-pads
289
290  - if:
291      properties:
292        phy_type:
293          const: ulpi
294
295    then:
296      properties:
297        reg:
298          minItems: 1
299          maxItems: 1
300
301        clocks:
302          minItems: 2
303          maxItems: 3
304
305        clock-names:
306          minItems: 2
307          maxItems: 3
308
309          oneOf:
310            - items:
311                - const: reg
312                - const: pll_u
313
314            - items:
315                - const: reg
316                - const: pll_u
317                - const: ulpi-link
318
319        resets:
320          minItems: 1
321          maxItems: 2
322
323        reset-names:
324          minItems: 1
325          maxItems: 2
326
327examples:
328  - |
329    #include <dt-bindings/clock/tegra124-car.h>
330
331    usb-phy@7d008000 {
332        compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
333        reg = <0x7d008000 0x4000>,
334              <0x7d000000 0x4000>;
335        interrupts = <0 97 4>;
336        phy_type = "utmi";
337        clocks = <&tegra_car TEGRA124_CLK_USB3>,
338                 <&tegra_car TEGRA124_CLK_PLL_U>,
339                 <&tegra_car TEGRA124_CLK_USBD>;
340        clock-names = "reg", "pll_u", "utmi-pads";
341        resets = <&tegra_car 59>, <&tegra_car 22>;
342        reset-names = "usb", "utmi-pads";
343        #phy-cells = <0>;
344        nvidia,hssync-start-delay = <0>;
345        nvidia,idle-wait-delay = <17>;
346        nvidia,elastic-limit = <16>;
347        nvidia,term-range-adj = <6>;
348        nvidia,xcvr-setup = <9>;
349        nvidia,xcvr-lsfslew = <0>;
350        nvidia,xcvr-lsrslew = <3>;
351        nvidia,hssquelch-level = <2>;
352        nvidia,hsdiscon-level = <5>;
353        nvidia,xcvr-hsslew = <12>;
354        nvidia,pmc = <&tegra_pmc 2>;
355    };
356
357  - |
358    #include <dt-bindings/clock/tegra20-car.h>
359
360    usb-phy@c5004000 {
361        compatible = "nvidia,tegra20-usb-phy";
362        reg = <0xc5004000 0x4000>;
363        interrupts = <0 21 4>;
364        phy_type = "ulpi";
365        clocks = <&tegra_car TEGRA20_CLK_USB2>,
366                 <&tegra_car TEGRA20_CLK_PLL_U>,
367                 <&tegra_car TEGRA20_CLK_CDEV2>;
368        clock-names = "reg", "pll_u", "ulpi-link";
369        resets = <&tegra_car 58>, <&tegra_car 22>;
370        reset-names = "usb", "utmi-pads";
371        #phy-cells = <0>;
372        nvidia,pmc = <&tegra_pmc 1>;
373    };
374