xref: /linux/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra USB PHY
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14properties:
15  compatible:
16    oneOf:
17      - items:
18          - enum:
19              - nvidia,tegra210-usb-phy
20              - nvidia,tegra124-usb-phy
21              - nvidia,tegra114-usb-phy
22          - enum:
23              - nvidia,tegra30-usb-phy
24      - items:
25          - enum:
26              - nvidia,tegra30-usb-phy
27              - nvidia,tegra20-usb-phy
28
29  reg:
30    minItems: 1
31    maxItems: 2
32    description: |
33      PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
34      PHY0 and PHY2 must specify two register sets, where the first set is
35      PHY own registers and the second set is the PHY0 registers.
36
37  clocks:
38    anyOf:
39      - items:
40          - description: Registers clock
41          - description: Main PHY clock
42
43      - items:
44          - description: Registers clock
45          - description: Main PHY clock
46          - description: ULPI PHY clock
47
48      - items:
49          - description: Registers clock
50          - description: Main PHY clock
51          - description: UTMI pads control registers clock
52
53      - items:
54          - description: Registers clock
55          - description: Main PHY clock
56          - description: UTMI timeout clock
57          - description: UTMI pads control registers clock
58
59  clock-names:
60    oneOf:
61      - items:
62          - const: reg
63          - const: pll_u
64
65      - items:
66          - const: reg
67          - const: pll_u
68          - const: ulpi-link
69
70      - items:
71          - const: reg
72          - const: pll_u
73          - const: utmi-pads
74
75      - items:
76          - const: reg
77          - const: pll_u
78          - const: timer
79          - const: utmi-pads
80
81  interrupts:
82    maxItems: 1
83
84  resets:
85    oneOf:
86      - maxItems: 1
87        description: PHY reset
88
89      - items:
90          - description: PHY reset
91          - description: UTMI pads reset
92
93  reset-names:
94    oneOf:
95      - const: usb
96
97      - items:
98          - const: usb
99          - const: utmi-pads
100
101  "#phy-cells":
102    const: 0
103
104  phy_type:
105    $ref: /schemas/types.yaml#/definitions/string
106    enum: [utmi, ulpi, hsic]
107
108  dr_mode:
109    $ref: /schemas/types.yaml#/definitions/string
110    enum: [host, peripheral, otg]
111    default: host
112
113  vbus-supply:
114    description: Regulator controlling USB VBUS.
115
116  nvidia,has-legacy-mode:
117    description: |
118      Indicates whether this controller can operate in legacy mode
119      (as APX 2500 / 2600). In legacy mode some registers are accessed
120      through the APB_MISC base address instead of the USB controller.
121    type: boolean
122
123  nvidia,is-wired:
124    description: |
125      Indicates whether we can do certain kind of power optimizations for
126      the devices that are always connected. e.g. modem.
127    type: boolean
128
129  nvidia,has-utmi-pad-registers:
130    description: |
131      Indicates whether this controller contains the UTMI pad control
132      registers common to all USB controllers.
133    type: boolean
134
135  nvidia,hssync-start-delay:
136    $ref: /schemas/types.yaml#/definitions/uint32
137    minimum: 0
138    maximum: 31
139    description: |
140      Number of 480 MHz clock cycles to wait before start of sync launches
141      RxActive.
142
143  nvidia,elastic-limit:
144    $ref: /schemas/types.yaml#/definitions/uint32
145    minimum: 0
146    maximum: 31
147    description: Variable FIFO Depth of elastic input store.
148
149  nvidia,idle-wait-delay:
150    $ref: /schemas/types.yaml#/definitions/uint32
151    minimum: 0
152    maximum: 31
153    description: |
154      Number of 480 MHz clock cycles of idle to wait before declare IDLE.
155
156  nvidia,term-range-adj:
157    $ref: /schemas/types.yaml#/definitions/uint32
158    minimum: 0
159    maximum: 15
160    description: Range adjustment on terminations.
161
162  nvidia,xcvr-setup:
163    $ref: /schemas/types.yaml#/definitions/uint32
164    minimum: 0
165    maximum: 127
166    description: Input of XCVR cell, HS driver output control.
167
168  nvidia,xcvr-setup-use-fuses:
169    description: Indicates that the value is read from the on-chip fuses.
170    type: boolean
171
172  nvidia,xcvr-lsfslew:
173    $ref: /schemas/types.yaml#/definitions/uint32
174    minimum: 0
175    maximum: 3
176    description: LS falling slew rate control.
177
178  nvidia,xcvr-lsrslew:
179    $ref: /schemas/types.yaml#/definitions/uint32
180    minimum: 0
181    maximum: 3
182    description: LS rising slew rate control.
183
184  nvidia,xcvr-hsslew:
185    $ref: /schemas/types.yaml#/definitions/uint32
186    minimum: 0
187    maximum: 511
188    description: HS slew rate control.
189
190  nvidia,hssquelch-level:
191    $ref: /schemas/types.yaml#/definitions/uint32
192    minimum: 0
193    maximum: 3
194    description: HS squelch detector level.
195
196  nvidia,hsdiscon-level:
197    $ref: /schemas/types.yaml#/definitions/uint32
198    minimum: 0
199    maximum: 7
200    description: HS disconnect detector level.
201
202  nvidia,phy-reset-gpio:
203    maxItems: 1
204    description: GPIO used to reset the PHY.
205
206  nvidia,pmc:
207    $ref: /schemas/types.yaml#/definitions/phandle-array
208    items:
209      - items:
210          - description: Phandle to Power Management controller.
211          - description: USB controller ID.
212    description:
213      Phandle to Power Management controller.
214
215required:
216  - compatible
217  - reg
218  - clocks
219  - clock-names
220  - resets
221  - reset-names
222  - "#phy-cells"
223  - phy_type
224
225additionalProperties: false
226
227allOf:
228  - if:
229      properties:
230        phy_type:
231          const: utmi
232
233    then:
234      properties:
235        reg:
236          minItems: 2
237          maxItems: 2
238
239        resets:
240          maxItems: 2
241
242        reset-names:
243          maxItems: 2
244
245      required:
246        - nvidia,hssync-start-delay
247        - nvidia,elastic-limit
248        - nvidia,idle-wait-delay
249        - nvidia,term-range-adj
250        - nvidia,xcvr-lsfslew
251        - nvidia,xcvr-lsrslew
252
253      anyOf:
254        - required: ["nvidia,xcvr-setup"]
255        - required: ["nvidia,xcvr-setup-use-fuses"]
256
257      if:
258        properties:
259          compatible:
260            contains:
261              const: nvidia,tegra30-usb-phy
262
263      then:
264        properties:
265          clocks:
266            maxItems: 3
267
268          clock-names:
269            items:
270              - const: reg
271              - const: pll_u
272              - const: utmi-pads
273
274        required:
275          - nvidia,xcvr-hsslew
276          - nvidia,hssquelch-level
277          - nvidia,hsdiscon-level
278
279      else:
280        properties:
281          clocks:
282            maxItems: 4
283
284          clock-names:
285            items:
286              - const: reg
287              - const: pll_u
288              - const: timer
289              - const: utmi-pads
290
291  - if:
292      properties:
293        phy_type:
294          const: ulpi
295
296    then:
297      properties:
298        reg:
299          minItems: 1
300          maxItems: 1
301
302        clocks:
303          minItems: 2
304          maxItems: 3
305
306        clock-names:
307          minItems: 2
308          maxItems: 3
309
310          oneOf:
311            - items:
312                - const: reg
313                - const: pll_u
314
315            - items:
316                - const: reg
317                - const: pll_u
318                - const: ulpi-link
319
320        resets:
321          minItems: 1
322          maxItems: 2
323
324        reset-names:
325          minItems: 1
326          maxItems: 2
327
328examples:
329  - |
330    #include <dt-bindings/clock/tegra124-car.h>
331
332    usb-phy@7d008000 {
333        compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
334        reg = <0x7d008000 0x4000>,
335              <0x7d000000 0x4000>;
336        interrupts = <0 97 4>;
337        phy_type = "utmi";
338        clocks = <&tegra_car TEGRA124_CLK_USB3>,
339                 <&tegra_car TEGRA124_CLK_PLL_U>,
340                 <&tegra_car TEGRA124_CLK_USBD>;
341        clock-names = "reg", "pll_u", "utmi-pads";
342        resets = <&tegra_car 59>, <&tegra_car 22>;
343        reset-names = "usb", "utmi-pads";
344        #phy-cells = <0>;
345        nvidia,hssync-start-delay = <0>;
346        nvidia,idle-wait-delay = <17>;
347        nvidia,elastic-limit = <16>;
348        nvidia,term-range-adj = <6>;
349        nvidia,xcvr-setup = <9>;
350        nvidia,xcvr-lsfslew = <0>;
351        nvidia,xcvr-lsrslew = <3>;
352        nvidia,hssquelch-level = <2>;
353        nvidia,hsdiscon-level = <5>;
354        nvidia,xcvr-hsslew = <12>;
355        nvidia,pmc = <&tegra_pmc 2>;
356    };
357
358  - |
359    #include <dt-bindings/clock/tegra20-car.h>
360
361    usb-phy@c5004000 {
362        compatible = "nvidia,tegra20-usb-phy";
363        reg = <0xc5004000 0x4000>;
364        interrupts = <0 21 4>;
365        phy_type = "ulpi";
366        clocks = <&tegra_car TEGRA20_CLK_USB2>,
367                 <&tegra_car TEGRA20_CLK_PLL_U>,
368                 <&tegra_car TEGRA20_CLK_CDEV2>;
369        clock-names = "reg", "pll_u", "ulpi-link";
370        resets = <&tegra_car 58>, <&tegra_car 22>;
371        reset-names = "usb", "utmi-pads";
372        #phy-cells = <0>;
373        nvidia,pmc = <&tegra_pmc 1>;
374    };
375