xref: /linux/Documentation/devicetree/bindings/phy/mscc,vsc7514-serdes.yaml (revision 1aca5ce036e3499336d1a2ace3070f908381c055) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microsemi Ocelot SerDes muxing
8
9maintainers:
10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
11  - UNGLinuxDriver@microchip.com
12
13description: |
14  On Microsemi Ocelot, there is a handful of registers in HSIO address
15  space for setting up the SerDes to switch port muxing.
16
17  A SerDes X can be "muxed" to work with switch port Y or Z for example.
18  One specific SerDes can also be used as a PCIe interface.
19
20  Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
21
22  There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
23  half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
24  10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
25
26  Also, SERDES6G number (aka "macro") 0 is the only interface supporting
27  QSGMII.
28
29  This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
30  Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
31
32properties:
33  compatible:
34    enum:
35      - mscc,vsc7514-serdes
36
37  "#phy-cells":
38    const: 2
39    description: |
40      The first number defines the input port to use for a given SerDes macro.
41      The second defines the macro to use. They are defined in
42      dt-bindings/phy/phy-ocelot-serdes.h
43
44required:
45  - compatible
46  - "#phy-cells"
47
48additionalProperties:
49  false
50
51examples:
52  - |
53    serdes: serdes {
54      compatible = "mscc,vsc7514-serdes";
55      #phy-cells = <2>;
56    };
57