xref: /linux/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek XS-PHY Controller
9
10maintainers:
11  - Chunfeng Yun <chunfeng.yun@mediatek.com>
12
13description: |
14  The XS-PHY controller supports physical layer functionality for USB3.1
15  GEN2 controller on MediaTek SoCs.
16
17  Banks layout of xsphy
18  ----------------------------------
19  port        offset    bank
20  u2 port0    0x0000    MISC
21              0x0100    FMREG
22              0x0300    U2PHY_COM
23  u2 port1    0x1000    MISC
24              0x1100    FMREG
25              0x1300    U2PHY_COM
26  u2 port2    0x2000    MISC
27              ...
28  u31 common  0x3000    DIG_GLB
29              0x3100    PHYA_GLB
30  u31 port0   0x3400    DIG_LN_TOP
31              0x3500    DIG_LN_TX0
32              0x3600    DIG_LN_RX0
33              0x3700    DIG_LN_DAIF
34              0x3800    PHYA_LN
35  u31 port1   0x3a00    DIG_LN_TOP
36              0x3b00    DIG_LN_TX0
37              0x3c00    DIG_LN_RX0
38              0x3d00    DIG_LN_DAIF
39              0x3e00    PHYA_LN
40              ...
41  DIG_GLB & PHYA_GLB are shared by U31 ports.
42
43properties:
44  $nodename:
45    pattern: "^xs-phy@[0-9a-f]+$"
46
47  compatible:
48    items:
49      - enum:
50          - mediatek,mt3611-xsphy
51          - mediatek,mt3612-xsphy
52          - mediatek,mt7988-xsphy
53      - const: mediatek,xsphy
54
55  reg:
56    description:
57      Register shared by multiple U3 ports, exclude port's private register,
58      if only U2 ports provided, shouldn't use the property.
59    maxItems: 1
60
61  "#address-cells":
62    enum: [1, 2]
63
64  "#size-cells":
65    enum: [1, 2]
66
67  ranges: true
68
69  mediatek,src-ref-clk-mhz:
70    description:
71      Frequency of reference clock for slew rate calibrate
72    default: 26
73
74  mediatek,src-coef:
75    description:
76      Coefficient for slew rate calibrate, depends on SoC process
77    $ref: /schemas/types.yaml#/definitions/uint32
78    default: 17
79
80# Required child node:
81patternProperties:
82  "^usb-phy@[0-9a-f]+$":
83    type: object
84    description:
85      A sub-node is required for each port the controller provides.
86      Address range information including the usual 'reg' property
87      is used inside these nodes to describe the controller's topology.
88
89    properties:
90      reg:
91        maxItems: 1
92
93      clocks:
94        items:
95          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
96
97      clock-names:
98        items:
99          - const: ref
100
101      "#phy-cells":
102        const: 1
103        description: |
104          The cells contain the following arguments.
105
106          - description: The PHY type
107              enum:
108                - PHY_TYPE_USB2
109                - PHY_TYPE_USB3
110
111      # The following optional vendor properties are only for debug or HQA test
112      mediatek,eye-src:
113        description:
114          The value of slew rate calibrate (U2 phy)
115        $ref: /schemas/types.yaml#/definitions/uint32
116        minimum: 1
117        maximum: 7
118
119      mediatek,eye-vrt:
120        description:
121          The selection of VRT reference voltage (U2 phy)
122        $ref: /schemas/types.yaml#/definitions/uint32
123        minimum: 1
124        maximum: 7
125
126      mediatek,eye-term:
127        description:
128          The selection of HS_TX TERM reference voltage (U2 phy)
129        $ref: /schemas/types.yaml#/definitions/uint32
130        minimum: 1
131        maximum: 7
132
133      mediatek,efuse-intr:
134        description:
135          The selection of Internal Resistor (U2/U3 phy)
136        $ref: /schemas/types.yaml#/definitions/uint32
137        minimum: 1
138        maximum: 63
139
140      mediatek,efuse-tx-imp:
141        description:
142          The selection of TX Impedance (U3 phy)
143        $ref: /schemas/types.yaml#/definitions/uint32
144        minimum: 1
145        maximum: 31
146
147      mediatek,efuse-rx-imp:
148        description:
149          The selection of RX Impedance (U3 phy)
150        $ref: /schemas/types.yaml#/definitions/uint32
151        minimum: 1
152        maximum: 31
153
154      mediatek,syscon-type:
155        $ref: /schemas/types.yaml#/definitions/phandle-array
156        description:
157          A phandle to syscon used to access the register of type switch,
158          the field should always be 3 cells long.
159        items:
160          - items:
161              - description:
162                  Phandle to phy type configuration system controller
163              - description:
164                  Phy type configuration register offset
165              - description:
166                  Index of config segment
167                enum: [0, 1, 2, 3]
168
169    required:
170      - reg
171      - clocks
172      - clock-names
173      - "#phy-cells"
174
175    additionalProperties: false
176
177required:
178  - compatible
179  - "#address-cells"
180  - "#size-cells"
181  - ranges
182
183additionalProperties: false
184
185examples:
186  - |
187    #include <dt-bindings/phy/phy.h>
188
189    u3phy: xs-phy@11c40000 {
190        compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
191        reg = <0x11c43000 0x0200>;
192        mediatek,src-ref-clk-mhz = <26>;
193        mediatek,src-coef = <17>;
194        #address-cells = <1>;
195        #size-cells = <1>;
196        ranges;
197
198        u2port0: usb-phy@11c40000 {
199            reg = <0x11c40000 0x0400>;
200            clocks = <&clk48m>;
201            clock-names = "ref";
202            mediatek,eye-src = <4>;
203            #phy-cells = <1>;
204        };
205
206        u3port0: usb-phy@11c43000 {
207            reg = <0x11c43400 0x0500>;
208            clocks = <&clk26m>;
209            clock-names = "ref";
210            mediatek,efuse-intr = <28>;
211            #phy-cells = <1>;
212        };
213    };
214
215...
216