1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller Device Tree Bindings 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy@[0-9a-f]+$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt7629-tphy 82 - mediatek,mt8183-tphy 83 - mediatek,mt8186-tphy 84 - mediatek,mt8192-tphy 85 - mediatek,mt8365-tphy 86 - const: mediatek,generic-tphy-v2 87 - items: 88 - enum: 89 - mediatek,mt8195-tphy 90 - const: mediatek,generic-tphy-v3 91 - const: mediatek,mt2701-u3phy 92 deprecated: true 93 - const: mediatek,mt2712-u3phy 94 deprecated: true 95 - const: mediatek,mt8173-u3phy 96 97 reg: 98 description: 99 Register shared by multiple ports, exclude port's private register. 100 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 101 T-PHY V2/V3, such as mt2712. 102 maxItems: 1 103 104 "#address-cells": 105 enum: [1, 2] 106 107 "#size-cells": 108 enum: [1, 2] 109 110 # Used with non-empty value if optional 'reg' is not provided. 111 # The format of the value is an arbitrary number of triplets of 112 # (child-bus-address, parent-bus-address, length). 113 ranges: true 114 115 mediatek,src-ref-clk-mhz: 116 description: 117 Frequency of reference clock for slew rate calibrate 118 default: 26 119 120 mediatek,src-coef: 121 description: 122 Coefficient for slew rate calibrate, depends on SoC process 123 $ref: /schemas/types.yaml#/definitions/uint32 124 default: 28 125 126# Required child node: 127patternProperties: 128 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 129 type: object 130 description: 131 A sub-node is required for each port the controller provides. 132 Address range information including the usual 'reg' property 133 is used inside these nodes to describe the controller's topology. 134 135 properties: 136 reg: 137 maxItems: 1 138 139 clocks: 140 minItems: 1 141 items: 142 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 143 - description: Reference clock of analog phy 144 description: 145 Uses both clocks if the clock of analog and digital phys are 146 separated, otherwise uses "ref" clock only if needed. 147 148 clock-names: 149 minItems: 1 150 items: 151 - const: ref 152 - const: da_ref 153 154 "#phy-cells": 155 const: 1 156 description: | 157 The cells contain the following arguments. 158 159 - description: The PHY type 160 enum: 161 - PHY_TYPE_USB2 162 - PHY_TYPE_USB3 163 - PHY_TYPE_PCIE 164 - PHY_TYPE_SATA 165 166 nvmem-cells: 167 items: 168 - description: internal R efuse for U2 PHY or U3/PCIe PHY 169 - description: rx_imp_sel efuse for U3/PCIe PHY 170 - description: tx_imp_sel efuse for U3/PCIe PHY 171 description: | 172 Phandles to nvmem cell that contains the efuse data; 173 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 174 three items should be provided at the same time for U3/PCIe PHY, 175 when use software to load efuse; 176 If unspecified, will use hardware auto-load efuse. 177 178 nvmem-cell-names: 179 items: 180 - const: intr 181 - const: rx_imp 182 - const: tx_imp 183 184 # The following optional vendor properties are only for debug or HQA test 185 mediatek,eye-src: 186 description: 187 The value of slew rate calibrate (U2 phy) 188 $ref: /schemas/types.yaml#/definitions/uint32 189 minimum: 1 190 maximum: 7 191 192 mediatek,eye-vrt: 193 description: 194 The selection of VRT reference voltage (U2 phy) 195 $ref: /schemas/types.yaml#/definitions/uint32 196 minimum: 1 197 maximum: 7 198 199 mediatek,eye-term: 200 description: 201 The selection of HS_TX TERM reference voltage (U2 phy) 202 $ref: /schemas/types.yaml#/definitions/uint32 203 minimum: 1 204 maximum: 7 205 206 mediatek,intr: 207 description: 208 The selection of internal resistor (U2 phy) 209 $ref: /schemas/types.yaml#/definitions/uint32 210 minimum: 1 211 maximum: 31 212 213 mediatek,discth: 214 description: 215 The selection of disconnect threshold (U2 phy) 216 $ref: /schemas/types.yaml#/definitions/uint32 217 minimum: 1 218 maximum: 15 219 220 mediatek,bc12: 221 description: 222 Specify the flag to enable BC1.2 if support it 223 type: boolean 224 225 mediatek,syscon-type: 226 $ref: /schemas/types.yaml#/definitions/phandle-array 227 maxItems: 1 228 description: 229 A phandle to syscon used to access the register of type switch, 230 the field should always be 3 cells long. 231 items: 232 items: 233 - description: 234 The first cell represents a phandle to syscon 235 - description: 236 The second cell represents the register offset 237 - description: 238 The third cell represents the index of config segment 239 enum: [0, 1, 2, 3] 240 241 required: 242 - reg 243 - "#phy-cells" 244 245 additionalProperties: false 246 247required: 248 - compatible 249 - "#address-cells" 250 - "#size-cells" 251 - ranges 252 253additionalProperties: false 254 255examples: 256 - | 257 #include <dt-bindings/clock/mt8173-clk.h> 258 #include <dt-bindings/interrupt-controller/arm-gic.h> 259 #include <dt-bindings/interrupt-controller/irq.h> 260 #include <dt-bindings/phy/phy.h> 261 usb@11271000 { 262 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 263 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 264 reg-names = "mac", "ippc"; 265 phys = <&u2port0 PHY_TYPE_USB2>, 266 <&u3port0 PHY_TYPE_USB3>, 267 <&u2port1 PHY_TYPE_USB2>; 268 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 269 clocks = <&topckgen CLK_TOP_USB30_SEL>; 270 clock-names = "sys_ck"; 271 }; 272 273 t-phy@11290000 { 274 compatible = "mediatek,mt8173-u3phy"; 275 reg = <0x11290000 0x800>; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 ranges; 279 280 u2port0: usb-phy@11290800 { 281 reg = <0x11290800 0x100>; 282 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 283 clock-names = "ref", "da_ref"; 284 #phy-cells = <1>; 285 }; 286 287 u3port0: usb-phy@11290900 { 288 reg = <0x11290900 0x700>; 289 clocks = <&clk26m>; 290 clock-names = "ref"; 291 #phy-cells = <1>; 292 }; 293 294 u2port1: usb-phy@11291000 { 295 reg = <0x11291000 0x100>; 296 #phy-cells = <1>; 297 }; 298 }; 299 300... 301