1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy(@[0-9a-f]+)?$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt6893-tphy 82 - mediatek,mt7629-tphy 83 - mediatek,mt7986-tphy 84 - mediatek,mt8183-tphy 85 - mediatek,mt8186-tphy 86 - mediatek,mt8192-tphy 87 - mediatek,mt8365-tphy 88 - const: mediatek,generic-tphy-v2 89 - items: 90 - enum: 91 - mediatek,mt8188-tphy 92 - mediatek,mt8195-tphy 93 - const: mediatek,generic-tphy-v3 94 - const: mediatek,mt2701-u3phy 95 deprecated: true 96 - const: mediatek,mt2712-u3phy 97 deprecated: true 98 - const: mediatek,mt8173-u3phy 99 100 reg: 101 description: 102 Register shared by multiple ports, exclude port's private register. 103 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 104 T-PHY V2/V3, such as mt2712. 105 maxItems: 1 106 107 "#address-cells": 108 enum: [1, 2] 109 110 "#size-cells": 111 enum: [1, 2] 112 113 # Used with non-empty value if optional 'reg' is not provided. 114 # The format of the value is an arbitrary number of triplets of 115 # (child-bus-address, parent-bus-address, length). 116 ranges: true 117 118 mediatek,src-ref-clk-mhz: 119 description: 120 Frequency of reference clock for slew rate calibrate 121 default: 26 122 123 mediatek,src-coef: 124 description: 125 Coefficient for slew rate calibrate, depends on SoC process 126 $ref: /schemas/types.yaml#/definitions/uint32 127 default: 28 128 129 power-domains: 130 description: 131 The TPHY of MediaTek should exist within a power domain. The 132 developer should be aware that the hardware design of MediaTek TPHY 133 does not require the addition of MTCMOS. If the power to the TPHY 134 is turned off, it will impact other functions. From the current 135 perspective of USB hardware design, even if MTCMOS is added to the 136 TPHY, it should remain always on. 137 maxItems: 1 138 139# Required child node: 140patternProperties: 141 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 142 type: object 143 description: 144 A sub-node is required for each port the controller provides. 145 Address range information including the usual 'reg' property 146 is used inside these nodes to describe the controller's topology. 147 148 properties: 149 reg: 150 maxItems: 1 151 152 clocks: 153 minItems: 1 154 items: 155 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 156 - description: Reference clock of analog phy 157 description: 158 Uses both clocks if the clock of analog and digital phys are 159 separated, otherwise uses "ref" clock only if needed. 160 161 clock-names: 162 minItems: 1 163 items: 164 - const: ref 165 - const: da_ref 166 167 "#phy-cells": 168 const: 1 169 description: | 170 The cells contain the following arguments. 171 172 - description: The PHY type 173 enum: 174 - PHY_TYPE_USB2 175 - PHY_TYPE_USB3 176 - PHY_TYPE_PCIE 177 - PHY_TYPE_SATA 178 - PHY_TYPE_SGMII 179 180 nvmem-cells: 181 items: 182 - description: internal R efuse for U2 PHY or U3/PCIe PHY 183 - description: rx_imp_sel efuse for U3/PCIe PHY 184 - description: tx_imp_sel efuse for U3/PCIe PHY 185 description: | 186 Phandles to nvmem cell that contains the efuse data; 187 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 188 three items should be provided at the same time for U3/PCIe PHY, 189 when use software to load efuse; 190 If unspecified, will use hardware auto-load efuse. 191 192 nvmem-cell-names: 193 items: 194 - const: intr 195 - const: rx_imp 196 - const: tx_imp 197 198 # The following optional vendor properties are only for debug or HQA test 199 mediatek,eye-src: 200 description: 201 The value of slew rate calibrate (U2 phy) 202 $ref: /schemas/types.yaml#/definitions/uint32 203 minimum: 1 204 maximum: 7 205 206 mediatek,eye-vrt: 207 description: 208 The selection of VRT reference voltage (U2 phy) 209 $ref: /schemas/types.yaml#/definitions/uint32 210 minimum: 1 211 maximum: 7 212 213 mediatek,eye-term: 214 description: 215 The selection of HS_TX TERM reference voltage (U2 phy) 216 $ref: /schemas/types.yaml#/definitions/uint32 217 minimum: 1 218 maximum: 7 219 220 mediatek,intr: 221 description: 222 The selection of internal resistor (U2 phy) 223 $ref: /schemas/types.yaml#/definitions/uint32 224 minimum: 1 225 maximum: 31 226 227 mediatek,discth: 228 description: 229 The selection of disconnect threshold (U2 phy) 230 $ref: /schemas/types.yaml#/definitions/uint32 231 minimum: 1 232 maximum: 15 233 234 mediatek,pre-emphasis: 235 description: 236 The level of pre-emphasis which used to widen the eye opening and 237 boost eye swing, the unit step is about 4.16% increment; e.g. the 238 level 1 means amplitude increases about 4.16%, the level 2 is about 239 8.3% etc. (U2 phy) 240 $ref: /schemas/types.yaml#/definitions/uint32 241 minimum: 1 242 maximum: 3 243 244 mediatek,bc12: 245 description: 246 Specify the flag to enable BC1.2 if support it 247 type: boolean 248 249 mediatek,force-mode: 250 description: 251 The force mode is used to manually switch the shared phy mode between 252 USB3 and PCIe, when USB3 phy type is selected by the consumer, and 253 force-mode is set, will cause phy's power and pipe toggled and force 254 phy as USB3 mode which switched from default PCIe mode. But prefer to 255 use the property "mediatek,syscon-type" for newer SoCs that support it. 256 type: boolean 257 258 mediatek,syscon-type: 259 $ref: /schemas/types.yaml#/definitions/phandle-array 260 maxItems: 1 261 description: 262 A phandle to syscon used to access the register of type switch, 263 the field should always be 3 cells long. 264 items: 265 items: 266 - description: 267 The first cell represents a phandle to syscon 268 - description: 269 The second cell represents the register offset 270 - description: 271 The third cell represents the index of config segment 272 enum: [0, 1, 2, 3] 273 274 required: 275 - reg 276 - "#phy-cells" 277 278 additionalProperties: false 279 280required: 281 - compatible 282 - "#address-cells" 283 - "#size-cells" 284 - ranges 285 286additionalProperties: false 287 288examples: 289 - | 290 #include <dt-bindings/clock/mt8173-clk.h> 291 #include <dt-bindings/interrupt-controller/arm-gic.h> 292 #include <dt-bindings/interrupt-controller/irq.h> 293 #include <dt-bindings/phy/phy.h> 294 usb@11271000 { 295 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 296 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 297 reg-names = "mac", "ippc"; 298 phys = <&u2port0 PHY_TYPE_USB2>, 299 <&u3port0 PHY_TYPE_USB3>, 300 <&u2port1 PHY_TYPE_USB2>; 301 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 302 clocks = <&topckgen CLK_TOP_USB30_SEL>; 303 clock-names = "sys_ck"; 304 }; 305 306 t-phy@11290000 { 307 compatible = "mediatek,mt8173-u3phy"; 308 reg = <0x11290000 0x800>; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 ranges; 312 313 u2port0: usb-phy@11290800 { 314 reg = <0x11290800 0x100>; 315 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 316 clock-names = "ref", "da_ref"; 317 #phy-cells = <1>; 318 }; 319 320 u3port0: usb-phy@11290900 { 321 reg = <0x11290900 0x700>; 322 clocks = <&clk26m>; 323 clock-names = "ref"; 324 #phy-cells = <1>; 325 }; 326 327 u2port1: usb-phy@11291000 { 328 reg = <0x11291000 0x100>; 329 #phy-cells = <1>; 330 }; 331 }; 332 333... 334