1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller Device Tree Bindings 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy@[0-9a-f]+$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt7629-tphy 82 - mediatek,mt8183-tphy 83 - const: mediatek,generic-tphy-v2 84 - items: 85 - enum: 86 - mediatek,mt8195-tphy 87 - const: mediatek,generic-tphy-v3 88 - const: mediatek,mt2701-u3phy 89 deprecated: true 90 - const: mediatek,mt2712-u3phy 91 deprecated: true 92 - const: mediatek,mt8173-u3phy 93 94 reg: 95 description: 96 Register shared by multiple ports, exclude port's private register. 97 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 98 T-PHY V2/V3, such as mt2712. 99 maxItems: 1 100 101 "#address-cells": 102 enum: [1, 2] 103 104 "#size-cells": 105 enum: [1, 2] 106 107 # Used with non-empty value if optional 'reg' is not provided. 108 # The format of the value is an arbitrary number of triplets of 109 # (child-bus-address, parent-bus-address, length). 110 ranges: true 111 112 mediatek,src-ref-clk-mhz: 113 description: 114 Frequency of reference clock for slew rate calibrate 115 default: 26 116 117 mediatek,src-coef: 118 description: 119 Coefficient for slew rate calibrate, depends on SoC process 120 $ref: /schemas/types.yaml#/definitions/uint32 121 default: 28 122 123# Required child node: 124patternProperties: 125 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 126 type: object 127 description: 128 A sub-node is required for each port the controller provides. 129 Address range information including the usual 'reg' property 130 is used inside these nodes to describe the controller's topology. 131 132 properties: 133 reg: 134 maxItems: 1 135 136 clocks: 137 minItems: 1 138 items: 139 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 140 - description: Reference clock of analog phy 141 description: 142 Uses both clocks if the clock of analog and digital phys are 143 separated, otherwise uses "ref" clock only if needed. 144 145 clock-names: 146 minItems: 1 147 items: 148 - const: ref 149 - const: da_ref 150 151 "#phy-cells": 152 const: 1 153 description: | 154 The cells contain the following arguments. 155 156 - description: The PHY type 157 enum: 158 - PHY_TYPE_USB2 159 - PHY_TYPE_USB3 160 - PHY_TYPE_PCIE 161 - PHY_TYPE_SATA 162 163 nvmem-cells: 164 items: 165 - description: internal R efuse for U2 PHY or U3/PCIe PHY 166 - description: rx_imp_sel efuse for U3/PCIe PHY 167 - description: tx_imp_sel efuse for U3/PCIe PHY 168 description: | 169 Phandles to nvmem cell that contains the efuse data; 170 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 171 three items should be provided at the same time for U3/PCIe PHY, 172 when use software to load efuse; 173 If unspecified, will use hardware auto-load efuse. 174 175 nvmem-cell-names: 176 items: 177 - const: intr 178 - const: rx_imp 179 - const: tx_imp 180 181 # The following optional vendor properties are only for debug or HQA test 182 mediatek,eye-src: 183 description: 184 The value of slew rate calibrate (U2 phy) 185 $ref: /schemas/types.yaml#/definitions/uint32 186 minimum: 1 187 maximum: 7 188 189 mediatek,eye-vrt: 190 description: 191 The selection of VRT reference voltage (U2 phy) 192 $ref: /schemas/types.yaml#/definitions/uint32 193 minimum: 1 194 maximum: 7 195 196 mediatek,eye-term: 197 description: 198 The selection of HS_TX TERM reference voltage (U2 phy) 199 $ref: /schemas/types.yaml#/definitions/uint32 200 minimum: 1 201 maximum: 7 202 203 mediatek,intr: 204 description: 205 The selection of internal resistor (U2 phy) 206 $ref: /schemas/types.yaml#/definitions/uint32 207 minimum: 1 208 maximum: 31 209 210 mediatek,discth: 211 description: 212 The selection of disconnect threshold (U2 phy) 213 $ref: /schemas/types.yaml#/definitions/uint32 214 minimum: 1 215 maximum: 15 216 217 mediatek,bc12: 218 description: 219 Specify the flag to enable BC1.2 if support it 220 type: boolean 221 222 mediatek,syscon-type: 223 $ref: /schemas/types.yaml#/definitions/phandle-array 224 maxItems: 1 225 description: 226 A phandle to syscon used to access the register of type switch, 227 the field should always be 3 cells long. 228 items: 229 items: 230 - description: 231 The first cell represents a phandle to syscon 232 - description: 233 The second cell represents the register offset 234 - description: 235 The third cell represents the index of config segment 236 enum: [0, 1, 2, 3] 237 238 required: 239 - reg 240 - "#phy-cells" 241 242 additionalProperties: false 243 244required: 245 - compatible 246 - "#address-cells" 247 - "#size-cells" 248 - ranges 249 250additionalProperties: false 251 252examples: 253 - | 254 #include <dt-bindings/clock/mt8173-clk.h> 255 #include <dt-bindings/interrupt-controller/arm-gic.h> 256 #include <dt-bindings/interrupt-controller/irq.h> 257 #include <dt-bindings/phy/phy.h> 258 usb@11271000 { 259 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 260 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 261 reg-names = "mac", "ippc"; 262 phys = <&u2port0 PHY_TYPE_USB2>, 263 <&u3port0 PHY_TYPE_USB3>, 264 <&u2port1 PHY_TYPE_USB2>; 265 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 266 clocks = <&topckgen CLK_TOP_USB30_SEL>; 267 clock-names = "sys_ck"; 268 }; 269 270 t-phy@11290000 { 271 compatible = "mediatek,mt8173-u3phy"; 272 reg = <0x11290000 0x800>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 ranges; 276 277 u2port0: usb-phy@11290800 { 278 reg = <0x11290800 0x100>; 279 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 280 clock-names = "ref", "da_ref"; 281 #phy-cells = <1>; 282 }; 283 284 u3port0: usb-phy@11290900 { 285 reg = <0x11290900 0x700>; 286 clocks = <&clk26m>; 287 clock-names = "ref"; 288 #phy-cells = <1>; 289 }; 290 291 u2port1: usb-phy@11291000 { 292 reg = <0x11291000 0x100>; 293 #phy-cells = <1>; 294 }; 295 }; 296 297... 298