1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy(@[0-9a-f]+)?$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt7629-tphy 82 - mediatek,mt7986-tphy 83 - mediatek,mt8183-tphy 84 - mediatek,mt8186-tphy 85 - mediatek,mt8192-tphy 86 - mediatek,mt8365-tphy 87 - const: mediatek,generic-tphy-v2 88 - items: 89 - enum: 90 - mediatek,mt8188-tphy 91 - mediatek,mt8195-tphy 92 - const: mediatek,generic-tphy-v3 93 - const: mediatek,mt2701-u3phy 94 deprecated: true 95 - const: mediatek,mt2712-u3phy 96 deprecated: true 97 - const: mediatek,mt8173-u3phy 98 99 reg: 100 description: 101 Register shared by multiple ports, exclude port's private register. 102 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 103 T-PHY V2/V3, such as mt2712. 104 maxItems: 1 105 106 "#address-cells": 107 enum: [1, 2] 108 109 "#size-cells": 110 enum: [1, 2] 111 112 # Used with non-empty value if optional 'reg' is not provided. 113 # The format of the value is an arbitrary number of triplets of 114 # (child-bus-address, parent-bus-address, length). 115 ranges: true 116 117 mediatek,src-ref-clk-mhz: 118 description: 119 Frequency of reference clock for slew rate calibrate 120 default: 26 121 122 mediatek,src-coef: 123 description: 124 Coefficient for slew rate calibrate, depends on SoC process 125 $ref: /schemas/types.yaml#/definitions/uint32 126 default: 28 127 128 power-domains: 129 description: 130 The TPHY of MediaTek should exist within a power domain. The 131 developer should be aware that the hardware design of MediaTek TPHY 132 does not require the addition of MTCMOS. If the power to the TPHY 133 is turned off, it will impact other functions. From the current 134 perspective of USB hardware design, even if MTCMOS is added to the 135 TPHY, it should remain always on. 136 maxItems: 1 137 138# Required child node: 139patternProperties: 140 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 141 type: object 142 description: 143 A sub-node is required for each port the controller provides. 144 Address range information including the usual 'reg' property 145 is used inside these nodes to describe the controller's topology. 146 147 properties: 148 reg: 149 maxItems: 1 150 151 clocks: 152 minItems: 1 153 items: 154 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 155 - description: Reference clock of analog phy 156 description: 157 Uses both clocks if the clock of analog and digital phys are 158 separated, otherwise uses "ref" clock only if needed. 159 160 clock-names: 161 minItems: 1 162 items: 163 - const: ref 164 - const: da_ref 165 166 "#phy-cells": 167 const: 1 168 description: | 169 The cells contain the following arguments. 170 171 - description: The PHY type 172 enum: 173 - PHY_TYPE_USB2 174 - PHY_TYPE_USB3 175 - PHY_TYPE_PCIE 176 - PHY_TYPE_SATA 177 - PHY_TYPE_SGMII 178 179 nvmem-cells: 180 items: 181 - description: internal R efuse for U2 PHY or U3/PCIe PHY 182 - description: rx_imp_sel efuse for U3/PCIe PHY 183 - description: tx_imp_sel efuse for U3/PCIe PHY 184 description: | 185 Phandles to nvmem cell that contains the efuse data; 186 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 187 three items should be provided at the same time for U3/PCIe PHY, 188 when use software to load efuse; 189 If unspecified, will use hardware auto-load efuse. 190 191 nvmem-cell-names: 192 items: 193 - const: intr 194 - const: rx_imp 195 - const: tx_imp 196 197 # The following optional vendor properties are only for debug or HQA test 198 mediatek,eye-src: 199 description: 200 The value of slew rate calibrate (U2 phy) 201 $ref: /schemas/types.yaml#/definitions/uint32 202 minimum: 1 203 maximum: 7 204 205 mediatek,eye-vrt: 206 description: 207 The selection of VRT reference voltage (U2 phy) 208 $ref: /schemas/types.yaml#/definitions/uint32 209 minimum: 1 210 maximum: 7 211 212 mediatek,eye-term: 213 description: 214 The selection of HS_TX TERM reference voltage (U2 phy) 215 $ref: /schemas/types.yaml#/definitions/uint32 216 minimum: 1 217 maximum: 7 218 219 mediatek,intr: 220 description: 221 The selection of internal resistor (U2 phy) 222 $ref: /schemas/types.yaml#/definitions/uint32 223 minimum: 1 224 maximum: 31 225 226 mediatek,discth: 227 description: 228 The selection of disconnect threshold (U2 phy) 229 $ref: /schemas/types.yaml#/definitions/uint32 230 minimum: 1 231 maximum: 15 232 233 mediatek,pre-emphasis: 234 description: 235 The level of pre-emphasis which used to widen the eye opening and 236 boost eye swing, the unit step is about 4.16% increment; e.g. the 237 level 1 means amplitude increases about 4.16%, the level 2 is about 238 8.3% etc. (U2 phy) 239 $ref: /schemas/types.yaml#/definitions/uint32 240 minimum: 1 241 maximum: 3 242 243 mediatek,bc12: 244 description: 245 Specify the flag to enable BC1.2 if support it 246 type: boolean 247 248 mediatek,force-mode: 249 description: 250 The force mode is used to manually switch the shared phy mode between 251 USB3 and PCIe, when USB3 phy type is selected by the consumer, and 252 force-mode is set, will cause phy's power and pipe toggled and force 253 phy as USB3 mode which switched from default PCIe mode. But prefer to 254 use the property "mediatek,syscon-type" for newer SoCs that support it. 255 type: boolean 256 257 mediatek,syscon-type: 258 $ref: /schemas/types.yaml#/definitions/phandle-array 259 maxItems: 1 260 description: 261 A phandle to syscon used to access the register of type switch, 262 the field should always be 3 cells long. 263 items: 264 items: 265 - description: 266 The first cell represents a phandle to syscon 267 - description: 268 The second cell represents the register offset 269 - description: 270 The third cell represents the index of config segment 271 enum: [0, 1, 2, 3] 272 273 required: 274 - reg 275 - "#phy-cells" 276 277 additionalProperties: false 278 279required: 280 - compatible 281 - "#address-cells" 282 - "#size-cells" 283 - ranges 284 285additionalProperties: false 286 287examples: 288 - | 289 #include <dt-bindings/clock/mt8173-clk.h> 290 #include <dt-bindings/interrupt-controller/arm-gic.h> 291 #include <dt-bindings/interrupt-controller/irq.h> 292 #include <dt-bindings/phy/phy.h> 293 usb@11271000 { 294 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 295 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 296 reg-names = "mac", "ippc"; 297 phys = <&u2port0 PHY_TYPE_USB2>, 298 <&u3port0 PHY_TYPE_USB3>, 299 <&u2port1 PHY_TYPE_USB2>; 300 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 301 clocks = <&topckgen CLK_TOP_USB30_SEL>; 302 clock-names = "sys_ck"; 303 }; 304 305 t-phy@11290000 { 306 compatible = "mediatek,mt8173-u3phy"; 307 reg = <0x11290000 0x800>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges; 311 312 u2port0: usb-phy@11290800 { 313 reg = <0x11290800 0x100>; 314 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 315 clock-names = "ref", "da_ref"; 316 #phy-cells = <1>; 317 }; 318 319 u3port0: usb-phy@11290900 { 320 reg = <0x11290900 0x700>; 321 clocks = <&clk26m>; 322 clock-names = "ref"; 323 #phy-cells = <1>; 324 }; 325 326 u2port1: usb-phy@11291000 { 327 reg = <0x11291000 0x100>; 328 #phy-cells = <1>; 329 }; 330 }; 331 332... 333