1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy(@[0-9a-f]+)?$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt6893-tphy 82 - mediatek,mt7629-tphy 83 - mediatek,mt7981-tphy 84 - mediatek,mt7986-tphy 85 - mediatek,mt8183-tphy 86 - mediatek,mt8186-tphy 87 - mediatek,mt8192-tphy 88 - mediatek,mt8365-tphy 89 - const: mediatek,generic-tphy-v2 90 - items: 91 - enum: 92 - mediatek,mt8188-tphy 93 - mediatek,mt8195-tphy 94 - const: mediatek,generic-tphy-v3 95 - const: mediatek,mt2701-u3phy 96 deprecated: true 97 - const: mediatek,mt2712-u3phy 98 deprecated: true 99 - const: mediatek,mt8173-u3phy 100 101 reg: 102 description: 103 Register shared by multiple ports, exclude port's private register. 104 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 105 T-PHY V2/V3, such as mt2712. 106 maxItems: 1 107 108 "#address-cells": 109 enum: [1, 2] 110 111 "#size-cells": 112 enum: [1, 2] 113 114 # Used with non-empty value if optional 'reg' is not provided. 115 # The format of the value is an arbitrary number of triplets of 116 # (child-bus-address, parent-bus-address, length). 117 ranges: true 118 119 mediatek,src-ref-clk-mhz: 120 description: 121 Frequency of reference clock for slew rate calibrate 122 default: 26 123 124 mediatek,src-coef: 125 description: 126 Coefficient for slew rate calibrate, depends on SoC process 127 $ref: /schemas/types.yaml#/definitions/uint32 128 default: 28 129 130 power-domains: 131 description: 132 The TPHY of MediaTek should exist within a power domain. The 133 developer should be aware that the hardware design of MediaTek TPHY 134 does not require the addition of MTCMOS. If the power to the TPHY 135 is turned off, it will impact other functions. From the current 136 perspective of USB hardware design, even if MTCMOS is added to the 137 TPHY, it should remain always on. 138 maxItems: 1 139 140# Required child node: 141patternProperties: 142 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 143 type: object 144 description: 145 A sub-node is required for each port the controller provides. 146 Address range information including the usual 'reg' property 147 is used inside these nodes to describe the controller's topology. 148 149 properties: 150 reg: 151 maxItems: 1 152 153 clocks: 154 minItems: 1 155 items: 156 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 157 - description: Reference clock of analog phy 158 description: 159 Uses both clocks if the clock of analog and digital phys are 160 separated, otherwise uses "ref" clock only if needed. 161 162 clock-names: 163 minItems: 1 164 items: 165 - const: ref 166 - const: da_ref 167 168 "#phy-cells": 169 const: 1 170 description: | 171 The cells contain the following arguments. 172 173 - description: The PHY type 174 enum: 175 - PHY_TYPE_USB2 176 - PHY_TYPE_USB3 177 - PHY_TYPE_PCIE 178 - PHY_TYPE_SATA 179 - PHY_TYPE_SGMII 180 181 nvmem-cells: 182 items: 183 - description: internal R efuse for U2 PHY or U3/PCIe PHY 184 - description: rx_imp_sel efuse for U3/PCIe PHY 185 - description: tx_imp_sel efuse for U3/PCIe PHY 186 description: | 187 Phandles to nvmem cell that contains the efuse data; 188 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 189 three items should be provided at the same time for U3/PCIe PHY, 190 when use software to load efuse; 191 If unspecified, will use hardware auto-load efuse. 192 193 nvmem-cell-names: 194 items: 195 - const: intr 196 - const: rx_imp 197 - const: tx_imp 198 199 # The following optional vendor properties are only for debug or HQA test 200 mediatek,eye-src: 201 description: 202 The value of slew rate calibrate (U2 phy) 203 $ref: /schemas/types.yaml#/definitions/uint32 204 minimum: 1 205 maximum: 7 206 207 mediatek,eye-vrt: 208 description: 209 The selection of VRT reference voltage (U2 phy) 210 $ref: /schemas/types.yaml#/definitions/uint32 211 minimum: 1 212 maximum: 7 213 214 mediatek,eye-term: 215 description: 216 The selection of HS_TX TERM reference voltage (U2 phy) 217 $ref: /schemas/types.yaml#/definitions/uint32 218 minimum: 1 219 maximum: 7 220 221 mediatek,intr: 222 description: 223 The selection of internal resistor (U2 phy) 224 $ref: /schemas/types.yaml#/definitions/uint32 225 minimum: 1 226 maximum: 31 227 228 mediatek,discth: 229 description: 230 The selection of disconnect threshold (U2 phy) 231 $ref: /schemas/types.yaml#/definitions/uint32 232 minimum: 1 233 maximum: 15 234 235 mediatek,pre-emphasis: 236 description: 237 The level of pre-emphasis which used to widen the eye opening and 238 boost eye swing, the unit step is about 4.16% increment; e.g. the 239 level 1 means amplitude increases about 4.16%, the level 2 is about 240 8.3% etc. (U2 phy) 241 $ref: /schemas/types.yaml#/definitions/uint32 242 minimum: 1 243 maximum: 3 244 245 mediatek,bc12: 246 description: 247 Specify the flag to enable BC1.2 if support it 248 type: boolean 249 250 mediatek,force-mode: 251 description: 252 The force mode is used to manually switch the shared phy mode between 253 USB3 and PCIe, when USB3 phy type is selected by the consumer, and 254 force-mode is set, will cause phy's power and pipe toggled and force 255 phy as USB3 mode which switched from default PCIe mode. But prefer to 256 use the property "mediatek,syscon-type" for newer SoCs that support it. 257 type: boolean 258 259 mediatek,syscon-type: 260 $ref: /schemas/types.yaml#/definitions/phandle-array 261 maxItems: 1 262 description: 263 A phandle to syscon used to access the register of type switch, 264 the field should always be 3 cells long. 265 items: 266 items: 267 - description: 268 The first cell represents a phandle to syscon 269 - description: 270 The second cell represents the register offset 271 - description: 272 The third cell represents the index of config segment 273 enum: [0, 1, 2, 3] 274 275 required: 276 - reg 277 - "#phy-cells" 278 279 additionalProperties: false 280 281required: 282 - compatible 283 - "#address-cells" 284 - "#size-cells" 285 - ranges 286 287additionalProperties: false 288 289examples: 290 - | 291 #include <dt-bindings/clock/mt8173-clk.h> 292 #include <dt-bindings/interrupt-controller/arm-gic.h> 293 #include <dt-bindings/interrupt-controller/irq.h> 294 #include <dt-bindings/phy/phy.h> 295 usb@11271000 { 296 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 297 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 298 reg-names = "mac", "ippc"; 299 phys = <&u2port0 PHY_TYPE_USB2>, 300 <&u3port0 PHY_TYPE_USB3>, 301 <&u2port1 PHY_TYPE_USB2>; 302 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 303 clocks = <&topckgen CLK_TOP_USB30_SEL>; 304 clock-names = "sys_ck"; 305 }; 306 307 t-phy@11290000 { 308 compatible = "mediatek,mt8173-u3phy"; 309 reg = <0x11290000 0x800>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 u2port0: usb-phy@11290800 { 315 reg = <0x11290800 0x100>; 316 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 317 clock-names = "ref", "da_ref"; 318 #phy-cells = <1>; 319 }; 320 321 u3port0: usb-phy@11290900 { 322 reg = <0x11290900 0x700>; 323 clocks = <&clk26m>; 324 clock-names = "ref"; 325 #phy-cells = <1>; 326 }; 327 328 u2port1: usb-phy@11291000 { 329 reg = <0x11291000 0x100>; 330 #phy-cells = <1>; 331 }; 332 }; 333 334... 335