xref: /linux/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml (revision e7d759f31ca295d589f7420719c311870bb3166f) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek PCIe PHY
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |
13  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
14
15properties:
16  compatible:
17    const: mediatek,mt8195-pcie-phy
18
19  reg:
20    maxItems: 1
21
22  reg-names:
23    items:
24      - const: sif
25
26  "#phy-cells":
27    const: 0
28
29  nvmem-cells:
30    maxItems: 7
31    description:
32      Phandles to nvmem cell that contains the efuse data, if unspecified,
33      default value is used.
34
35  nvmem-cell-names:
36    items:
37      - const: glb_intr
38      - const: tx_ln0_pmos
39      - const: tx_ln0_nmos
40      - const: rx_ln0
41      - const: tx_ln1_pmos
42      - const: tx_ln1_nmos
43      - const: rx_ln1
44
45  power-domains:
46    maxItems: 1
47
48required:
49  - compatible
50  - reg
51  - reg-names
52  - "#phy-cells"
53
54additionalProperties: false
55
56examples:
57  - |
58    phy@11e80000 {
59        compatible = "mediatek,mt8195-pcie-phy";
60        #phy-cells = <0>;
61        reg = <0x11e80000 0x10000>;
62        reg-names = "sif";
63        nvmem-cells = <&pciephy_glb_intr>,
64                      <&pciephy_tx_ln0_pmos>,
65                      <&pciephy_tx_ln0_nmos>,
66                      <&pciephy_rx_ln0>,
67                      <&pciephy_tx_ln1_pmos>,
68                      <&pciephy_tx_ln1_nmos>,
69                      <&pciephy_rx_ln1>;
70        nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
71                           "tx_ln0_nmos", "rx_ln0",
72                           "tx_ln1_pmos", "tx_ln1_nmos",
73                           "rx_ln1";
74        power-domains = <&spm 2>;
75    };
76