xref: /linux/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek High Definition Multimedia Interface (HDMI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: |
16  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17  output and drives the HDMI pads.
18
19properties:
20  $nodename:
21    pattern: "^hdmi-phy@[0-9a-f]+$"
22
23  compatible:
24    oneOf:
25      - items:
26          - enum:
27              - mediatek,mt7623-hdmi-phy
28          - const: mediatek,mt2701-hdmi-phy
29      - items:
30          - enum:
31              - mediatek,mt8188-hdmi-phy
32          - const: mediatek,mt8195-hdmi-phy
33      - const: mediatek,mt2701-hdmi-phy
34      - const: mediatek,mt8173-hdmi-phy
35      - const: mediatek,mt8195-hdmi-phy
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    items:
43      - description: PLL reference clock
44      - description: HDMI 26MHz clock
45      - description: HDMI PLL1 clock
46      - description: HDMI PLL2 clock
47
48  clock-names:
49    minItems: 1
50    items:
51      - const: pll_ref
52      - const: 26m
53      - const: pll1
54      - const: pll2
55
56  clock-output-names:
57    maxItems: 1
58
59  "#phy-cells":
60    const: 0
61
62  "#clock-cells":
63    const: 0
64
65  mediatek,ibias:
66    description:
67      TX DRV bias current for < 1.65Gbps
68    $ref: /schemas/types.yaml#/definitions/uint32
69    minimum: 0
70    maximum: 63
71    default: 0xa
72
73  mediatek,ibias_up:
74    description:
75      TX DRV bias current for >= 1.65Gbps
76    $ref: /schemas/types.yaml#/definitions/uint32
77    minimum: 0
78    maximum: 63
79    default: 0x1c
80
81required:
82  - compatible
83  - reg
84  - clocks
85  - clock-names
86  - clock-output-names
87  - "#phy-cells"
88  - "#clock-cells"
89
90allOf:
91  - if:
92      not:
93        properties:
94          compatible:
95            contains:
96              const: mediatek,mt8195-hdmi-phy
97    then:
98      properties:
99        clocks:
100          maxItems: 1
101        clock-names:
102          maxItems: 1
103
104additionalProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/clock/mt8173-clk.h>
109    hdmi_phy: hdmi-phy@10209100 {
110        compatible = "mediatek,mt8173-hdmi-phy";
111        reg = <0x10209100 0x24>;
112        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
113        clock-names = "pll_ref";
114        clock-output-names = "hdmitx_dig_cts";
115        mediatek,ibias = <0xa>;
116        mediatek,ibias_up = <0x1c>;
117        #clock-cells = <0>;
118        #phy-cells = <0>;
119    };
120
121...
122