xref: /linux/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml (revision 917b10d90990fd2138b5dbc2d22cfa428c070ade) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MIPI Display Serial Interface (DSI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: The MIPI DSI PHY supports up to 4-lane output.
16
17properties:
18  $nodename:
19    pattern: "^dsi-phy@[0-9a-f]+$"
20
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt7623-mipi-tx
26          - const: mediatek,mt2701-mipi-tx
27      - items:
28          - enum:
29              - mediatek,mt6795-mipi-tx
30          - const: mediatek,mt8173-mipi-tx
31      - items:
32          - enum:
33              - mediatek,mt6893-mipi-tx
34              - mediatek,mt8188-mipi-tx
35              - mediatek,mt8195-mipi-tx
36              - mediatek,mt8365-mipi-tx
37          - const: mediatek,mt8183-mipi-tx
38      - const: mediatek,mt2701-mipi-tx
39      - const: mediatek,mt8173-mipi-tx
40      - const: mediatek,mt8183-mipi-tx
41
42  reg:
43    maxItems: 1
44
45  clocks:
46    items:
47      - description: PLL reference clock
48
49  clock-output-names:
50    maxItems: 1
51
52  "#phy-cells":
53    const: 0
54
55  "#clock-cells":
56    const: 0
57
58  nvmem-cells:
59    maxItems: 1
60    description: A phandle to the calibration data provided by a nvmem device,
61      if unspecified, default values shall be used.
62
63  nvmem-cell-names:
64    items:
65      - const: calibration-data
66
67  drive-strength-microamp:
68    description: adjust driving current
69    multipleOf: 200
70    minimum: 2000
71    maximum: 6000
72    default: 4600
73
74required:
75  - compatible
76  - reg
77  - clocks
78  - clock-output-names
79  - "#phy-cells"
80  - "#clock-cells"
81
82additionalProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/mt8173-clk.h>
87    dsi-phy@10215000 {
88        compatible = "mediatek,mt8173-mipi-tx";
89        reg = <0x10215000 0x1000>;
90        clocks = <&clk26m>;
91        clock-output-names = "mipi_tx0_pll";
92        drive-strength-microamp = <4000>;
93        nvmem-cells = <&mipi_tx_calibration>;
94        nvmem-cell-names = "calibration-data";
95        #clock-cells = <0>;
96        #phy-cells = <0>;
97    };
98
99...
100