xref: /linux/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MIPI Display Serial Interface (DSI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: The MIPI DSI PHY supports up to 4-lane output.
16
17properties:
18  $nodename:
19    pattern: "^dsi-phy@[0-9a-f]+$"
20
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt7623-mipi-tx
26              - mediatek,mt8167-mipi-tx
27          - const: mediatek,mt2701-mipi-tx
28      - items:
29          - enum:
30              - mediatek,mt6795-mipi-tx
31          - const: mediatek,mt8173-mipi-tx
32      - items:
33          - enum:
34              - mediatek,mt6893-mipi-tx
35              - mediatek,mt8188-mipi-tx
36              - mediatek,mt8195-mipi-tx
37              - mediatek,mt8365-mipi-tx
38          - const: mediatek,mt8183-mipi-tx
39      - const: mediatek,mt2701-mipi-tx
40      - const: mediatek,mt8173-mipi-tx
41      - const: mediatek,mt8183-mipi-tx
42
43  reg:
44    maxItems: 1
45
46  clocks:
47    items:
48      - description: PLL reference clock
49
50  clock-output-names:
51    maxItems: 1
52
53  "#phy-cells":
54    const: 0
55
56  "#clock-cells":
57    const: 0
58
59  nvmem-cells:
60    maxItems: 1
61    description: A phandle to the calibration data provided by a nvmem device,
62      if unspecified, default values shall be used.
63
64  nvmem-cell-names:
65    items:
66      - const: calibration-data
67
68  drive-strength-microamp:
69    description: adjust driving current
70    multipleOf: 200
71    minimum: 2000
72    maximum: 6000
73    default: 4600
74
75required:
76  - compatible
77  - reg
78  - clocks
79  - clock-output-names
80  - "#phy-cells"
81  - "#clock-cells"
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/mt8173-clk.h>
88    dsi-phy@10215000 {
89        compatible = "mediatek,mt8173-mipi-tx";
90        reg = <0x10215000 0x1000>;
91        clocks = <&clk26m>;
92        clock-output-names = "mipi_tx0_pll";
93        drive-strength-microamp = <4000>;
94        nvmem-cells = <&mipi_tx_calibration>;
95        nvmem-cell-names = "calibration-data";
96        #clock-cells = <0>;
97        #phy-cells = <0>;
98    };
99
100...
101