xref: /linux/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MIPI Display Serial Interface (DSI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: The MIPI DSI PHY supports up to 4-lane output.
16
17properties:
18  $nodename:
19    pattern: "^dsi-phy@[0-9a-f]+$"
20
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt7623-mipi-tx
26              - mediatek,mt8167-mipi-tx
27          - const: mediatek,mt2701-mipi-tx
28      - items:
29          - enum:
30              - mediatek,mt6795-mipi-tx
31          - const: mediatek,mt8173-mipi-tx
32      - items:
33          - enum:
34              - mediatek,mt6893-mipi-tx
35              - mediatek,mt8188-mipi-tx
36              - mediatek,mt8195-mipi-tx
37              - mediatek,mt8365-mipi-tx
38          - const: mediatek,mt8183-mipi-tx
39      - const: mediatek,mt2701-mipi-tx
40      - const: mediatek,mt8173-mipi-tx
41      - const: mediatek,mt8183-mipi-tx
42      - const: mediatek,mt8196-mipi-tx
43
44  reg:
45    maxItems: 1
46
47  clocks:
48    items:
49      - description: PLL reference clock
50
51  clock-output-names:
52    maxItems: 1
53
54  "#phy-cells":
55    const: 0
56
57  "#clock-cells":
58    const: 0
59
60  nvmem-cells:
61    maxItems: 1
62    description: A phandle to the calibration data provided by a nvmem device,
63      if unspecified, default values shall be used.
64
65  nvmem-cell-names:
66    items:
67      - const: calibration-data
68
69  drive-strength-microamp:
70    description: adjust driving current
71    multipleOf: 200
72    minimum: 2000
73    maximum: 6000
74    default: 4600
75
76required:
77  - compatible
78  - reg
79  - clocks
80  - clock-output-names
81  - "#phy-cells"
82  - "#clock-cells"
83
84additionalProperties: false
85
86examples:
87  - |
88    #include <dt-bindings/clock/mt8173-clk.h>
89    dsi-phy@10215000 {
90        compatible = "mediatek,mt8173-mipi-tx";
91        reg = <0x10215000 0x1000>;
92        clocks = <&clk26m>;
93        clock-output-names = "mipi_tx0_pll";
94        drive-strength-microamp = <4000>;
95        nvmem-cells = <&mipi_tx_calibration>;
96        nvmem-cell-names = "calibration-data";
97        #clock-cells = <0>;
98        #phy-cells = <0>;
99    };
100
101...
102