xref: /linux/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MIPI Display Serial Interface (DSI) PHY
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: The MIPI DSI PHY supports up to 4-lane output.
16
17properties:
18  $nodename:
19    pattern: "^dsi-phy@[0-9a-f]+$"
20
21  compatible:
22    oneOf:
23      - items:
24          - enum:
25              - mediatek,mt7623-mipi-tx
26          - const: mediatek,mt2701-mipi-tx
27      - items:
28          - enum:
29              - mediatek,mt6795-mipi-tx
30          - const: mediatek,mt8173-mipi-tx
31      - items:
32          - enum:
33              - mediatek,mt8365-mipi-tx
34          - const: mediatek,mt8183-mipi-tx
35      - const: mediatek,mt2701-mipi-tx
36      - const: mediatek,mt8173-mipi-tx
37      - const: mediatek,mt8183-mipi-tx
38
39  reg:
40    maxItems: 1
41
42  clocks:
43    items:
44      - description: PLL reference clock
45
46  clock-output-names:
47    maxItems: 1
48
49  "#phy-cells":
50    const: 0
51
52  "#clock-cells":
53    const: 0
54
55  nvmem-cells:
56    maxItems: 1
57    description: A phandle to the calibration data provided by a nvmem device,
58      if unspecified, default values shall be used.
59
60  nvmem-cell-names:
61    items:
62      - const: calibration-data
63
64  drive-strength-microamp:
65    description: adjust driving current
66    multipleOf: 200
67    minimum: 2000
68    maximum: 6000
69    default: 4600
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-output-names
76  - "#phy-cells"
77  - "#clock-cells"
78
79additionalProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/clock/mt8173-clk.h>
84    dsi-phy@10215000 {
85        compatible = "mediatek,mt8173-mipi-tx";
86        reg = <0x10215000 0x1000>;
87        clocks = <&clk26m>;
88        clock-output-names = "mipi_tx0_pll";
89        drive-strength-microamp = <4000>;
90        nvmem-cells = <&mipi_tx_calibration>;
91        nvmem-cell-names = "calibration-data";
92        #clock-cells = <0>;
93        #phy-cells = <0>;
94    };
95
96...
97