167038ec1SChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 267038ec1SChunfeng Yun# Copyright (c) 2020 MediaTek 367038ec1SChunfeng Yun%YAML 1.2 467038ec1SChunfeng Yun--- 567038ec1SChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml# 667038ec1SChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 767038ec1SChunfeng Yun 867038ec1SChunfeng Yuntitle: MediaTek Universal Flash Storage (UFS) M-PHY binding 967038ec1SChunfeng Yun 1067038ec1SChunfeng Yunmaintainers: 1167038ec1SChunfeng Yun - Stanley Chu <stanley.chu@mediatek.com> 1267038ec1SChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 1367038ec1SChunfeng Yun 1467038ec1SChunfeng Yundescription: | 1567038ec1SChunfeng Yun UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 1667038ec1SChunfeng Yun Each UFS M-PHY node should have its own node. 1767038ec1SChunfeng Yun To bind UFS M-PHY with UFS host controller, the controller node should 1867038ec1SChunfeng Yun contain a phandle reference to UFS M-PHY node. 1967038ec1SChunfeng Yun 2067038ec1SChunfeng Yunproperties: 2167038ec1SChunfeng Yun $nodename: 2267038ec1SChunfeng Yun pattern: "^ufs-phy@[0-9a-f]+$" 2367038ec1SChunfeng Yun 2467038ec1SChunfeng Yun compatible: 25*d57cd79dSSeiya Wang oneOf: 26*d57cd79dSSeiya Wang - items: 27*d57cd79dSSeiya Wang - enum: 28*d57cd79dSSeiya Wang - mediatek,mt8195-ufsphy 29*d57cd79dSSeiya Wang - const: mediatek,mt8183-ufsphy 30*d57cd79dSSeiya Wang - const: mediatek,mt8183-ufsphy 3167038ec1SChunfeng Yun 3267038ec1SChunfeng Yun reg: 3367038ec1SChunfeng Yun maxItems: 1 3467038ec1SChunfeng Yun 3567038ec1SChunfeng Yun clocks: 3667038ec1SChunfeng Yun items: 3767038ec1SChunfeng Yun - description: Unipro core control clock. 3867038ec1SChunfeng Yun - description: M-PHY core control clock. 3967038ec1SChunfeng Yun 4067038ec1SChunfeng Yun clock-names: 4167038ec1SChunfeng Yun items: 4267038ec1SChunfeng Yun - const: unipro 4367038ec1SChunfeng Yun - const: mp 4467038ec1SChunfeng Yun 4567038ec1SChunfeng Yun "#phy-cells": 4667038ec1SChunfeng Yun const: 0 4767038ec1SChunfeng Yun 4867038ec1SChunfeng Yunrequired: 4967038ec1SChunfeng Yun - compatible 5067038ec1SChunfeng Yun - reg 5167038ec1SChunfeng Yun - "#phy-cells" 5267038ec1SChunfeng Yun - clocks 5367038ec1SChunfeng Yun - clock-names 5467038ec1SChunfeng Yun 5567038ec1SChunfeng YunadditionalProperties: false 5667038ec1SChunfeng Yun 5767038ec1SChunfeng Yunexamples: 5867038ec1SChunfeng Yun - | 5967038ec1SChunfeng Yun #include <dt-bindings/clock/mt8183-clk.h> 6067038ec1SChunfeng Yun ufsphy: ufs-phy@11fa0000 { 6167038ec1SChunfeng Yun compatible = "mediatek,mt8183-ufsphy"; 6267038ec1SChunfeng Yun reg = <0x11fa0000 0xc000>; 6367038ec1SChunfeng Yun clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 6467038ec1SChunfeng Yun <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>; 6567038ec1SChunfeng Yun clock-names = "unipro", "mp"; 6667038ec1SChunfeng Yun #phy-cells = <0>; 6767038ec1SChunfeng Yun }; 6867038ec1SChunfeng Yun 6967038ec1SChunfeng Yun... 70