1*67038ec1SChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*67038ec1SChunfeng Yun# Copyright (c) 2020 MediaTek 3*67038ec1SChunfeng Yun%YAML 1.2 4*67038ec1SChunfeng Yun--- 5*67038ec1SChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml# 6*67038ec1SChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*67038ec1SChunfeng Yun 8*67038ec1SChunfeng Yuntitle: MediaTek Universal Flash Storage (UFS) M-PHY binding 9*67038ec1SChunfeng Yun 10*67038ec1SChunfeng Yunmaintainers: 11*67038ec1SChunfeng Yun - Stanley Chu <stanley.chu@mediatek.com> 12*67038ec1SChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 13*67038ec1SChunfeng Yun 14*67038ec1SChunfeng Yundescription: | 15*67038ec1SChunfeng Yun UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 16*67038ec1SChunfeng Yun Each UFS M-PHY node should have its own node. 17*67038ec1SChunfeng Yun To bind UFS M-PHY with UFS host controller, the controller node should 18*67038ec1SChunfeng Yun contain a phandle reference to UFS M-PHY node. 19*67038ec1SChunfeng Yun 20*67038ec1SChunfeng Yunproperties: 21*67038ec1SChunfeng Yun $nodename: 22*67038ec1SChunfeng Yun pattern: "^ufs-phy@[0-9a-f]+$" 23*67038ec1SChunfeng Yun 24*67038ec1SChunfeng Yun compatible: 25*67038ec1SChunfeng Yun const: mediatek,mt8183-ufsphy 26*67038ec1SChunfeng Yun 27*67038ec1SChunfeng Yun reg: 28*67038ec1SChunfeng Yun maxItems: 1 29*67038ec1SChunfeng Yun 30*67038ec1SChunfeng Yun clocks: 31*67038ec1SChunfeng Yun items: 32*67038ec1SChunfeng Yun - description: Unipro core control clock. 33*67038ec1SChunfeng Yun - description: M-PHY core control clock. 34*67038ec1SChunfeng Yun 35*67038ec1SChunfeng Yun clock-names: 36*67038ec1SChunfeng Yun items: 37*67038ec1SChunfeng Yun - const: unipro 38*67038ec1SChunfeng Yun - const: mp 39*67038ec1SChunfeng Yun 40*67038ec1SChunfeng Yun "#phy-cells": 41*67038ec1SChunfeng Yun const: 0 42*67038ec1SChunfeng Yun 43*67038ec1SChunfeng Yunrequired: 44*67038ec1SChunfeng Yun - compatible 45*67038ec1SChunfeng Yun - reg 46*67038ec1SChunfeng Yun - "#phy-cells" 47*67038ec1SChunfeng Yun - clocks 48*67038ec1SChunfeng Yun - clock-names 49*67038ec1SChunfeng Yun 50*67038ec1SChunfeng YunadditionalProperties: false 51*67038ec1SChunfeng Yun 52*67038ec1SChunfeng Yunexamples: 53*67038ec1SChunfeng Yun - | 54*67038ec1SChunfeng Yun #include <dt-bindings/clock/mt8183-clk.h> 55*67038ec1SChunfeng Yun ufsphy: ufs-phy@11fa0000 { 56*67038ec1SChunfeng Yun compatible = "mediatek,mt8183-ufsphy"; 57*67038ec1SChunfeng Yun reg = <0x11fa0000 0xc000>; 58*67038ec1SChunfeng Yun clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 59*67038ec1SChunfeng Yun <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>; 60*67038ec1SChunfeng Yun clock-names = "unipro", "mp"; 61*67038ec1SChunfeng Yun #phy-cells = <0>; 62*67038ec1SChunfeng Yun }; 63*67038ec1SChunfeng Yun 64*67038ec1SChunfeng Yun... 65